[PATCH 3/4] dt-bindings: phy: airoha: Document support for AN7583 PCIe PHY
From: Christian Marangi <ansuelsmth@gmail.com>
Date: 2025-06-06 19:22:43
Also in:
linux-devicetree, linux-phy, lkml
Subsystem:
generic phy framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Document support for AN7583 PCIe PHY used to make the Gen3 PCIe port work. Add the rwquired register to configure the PCIe PHY and provide an example for it. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- .../bindings/phy/airoha,an7583-pcie-phy.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml
new file mode 100644
index 000000000000..93252092c2e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-phy.yaml@@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7583-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 PCI-Express PHY + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port. + +properties: + compatible: + const: airoha,an7583-pcie-phy + + reg: + items: + - description: PCIE G3 analog base address + - description: PCIE G3 PMA base address + - description: PCIE QPhy analog base address + - description: PCIE QPhy PMA base address + - description: PCIE QPhy diagnostic base address + - description: PCIE detection time base address + - description: PCIE Rx AEQ base address + + reg-names: + items: + - const: g3-ana + - const: g3-pma + - const: qp-ana + - const: qp-pma + - const: qp-dig + - const: xr-dtime + - const: rx-aeq + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/phy/phy.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@11e80000 { + compatible = "airoha,an7583-pcie-phy"; + #phy-cells = <0>; + reg = <0x0 0x1fc7f000 0x0 0xfff>, + <0x0 0x1fc7e000 0x0 0xfff>, + <0x0 0x1fa5f000 0x0 0xff>, + <0x0 0x1fa5e000 0x0 0x8ff>, + <0x0 0x1fa5a000 0x0 0x3ff>, + <0x0 0x1fc30044 0x0 0x4>, + <0x0 0x1fc35030 0x0 0x4>; + reg-names = "g3-ana", "g3-pma", + "qp-ana", "qp-pma", "qp-dig", + "xr-dtime", "rx-aeq"; + }; + };
--
2.48.1