On Sun, Jun 1, 2025 at 1:36 PM Marco Felsch [off-list ref] wrote:

Hi Adam,

thanks for the patch.

On 25-05-30, Adam Ford wrote:

quoted

The defaults for this SoC are configured for overdrive mode, but
the VPU clocks are currently configured for nominal mode.
Increase VPU_G1_CLK_ROOT to 800MHZ from 600MHz,
Increase VPU_G2_CLK_ROOT to 700MHZ from 500MHz, and
Increase VPU_BUS_CLK_ROOT to 800MHz from 600MHz.

This requires adjusting the clock parents. Since there is already
800MHz clock references, move the VPU_BUS and G1 clocks to it.
This frees up the VPU_PLL to be configured at 700MHz to run
the G2 clock at 700MHz.

Signed-off-by: Adam Ford <redacted>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 909555a5da4b..848b25c9b752 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi

@@ -2256,8 +2256,8 @@ vpu_g1: video-codec@38300000 {
                      interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                      clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
                      assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
-                     assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
-                     assigned-clock-rates = <600000000>;
+                     assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+                     assigned-clock-rates = <800000000>;
                      power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
              };

@@ -2267,8 +2267,8 @@ vpu_g2: video-codec@38310000 {
                      interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                      clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
                      assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
-                     assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
-                     assigned-clock-rates = <500000000>;
+                     assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
+                     assigned-clock-rates = <700000000>;
                      power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
              };

@@ -2284,8 +2284,8 @@ vpumix_blk_ctrl: blk-ctrl@38330000 {
                               <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
                      clock-names = "g1", "g2", "vc8000e";
                      assigned-clocks = <&clk IMX8MP_VPU_PLL>, <&clk IMX8MP_CLK_VPU_BUS>;
-                     assigned-clock-parents = <0>, <&clk IMX8MP_VPU_PLL_OUT>;
-                     assigned-clock-rates = <600000000>, <600000000>;
+                     assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL1_800M>;
+                     assigned-clock-rates = <700000000>, <800000000>;

I think we can drop the "assigned-clocks = <&clk IMX8MP_VPU_PLL>" part
completely.

Before your patch the IMX8MP_VPU_PLL_OUT was used as clock-parent for
the IMX8MP_CLK_VPU_BUS. With yout patch IMX8MP_SYS_PLL1_800M is used.

I think you're right.  I'll fix that up and do a V2.  I forgot to add
my own s-o-b tag, so I'll fix that too.  I'll try to do it this week.

adam

Regards,
  Marco