On 2025/5/13 16:04, Niklas Cassel wrote:

On Sat, May 10, 2025 at 11:56:06PM +0800, Hans Zhang wrote:

quoted

Current PCIe initialization logic may leave root ports operating with
non-optimal Maximum Payload Size (MPS) settings. While downstream device
configuration is handled during bus enumeration, root port MPS values
inherited from firmware or hardware defaults might not utilize the full
capabilities supported by the controller hardware. This can result is
uboptimal data transfer efficiency across the PCIe hierarchy.

During host controller probing phase, when PCIe bus tuning is enabled,
the implementation now configures root port MPS settings to their
hardware-supported maximum values. By iterating through bridge devices
under the root bus and identifying PCIe root ports, each port's MPS is
set to 128 << pcie_mpss to match the device's maximum supported payload
size. The Max Read Request Size (MRRS) is subsequently adjusted through
existing companion logic to maintain compatibility with PCIe
specifications.

Explicit initialization at host probing stage ensures consistent PCIe
topology configuration before downstream devices perform their own MPS
negotiations. This proactive approach addresses platform-specific
requirements where controller drivers depend on properly initialized
root port settings, while maintaining backward compatibility through
PCIE_BUS_TUNE_OFF conditional checks. Hardware capabilities are fully
utilized without altering existing device negotiation behaviors.

Suggested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Hans Zhang <18255117159@163.com>
---

Looks good to me, but since this I'm the one who suggested this specific
implementation, it would be good if someone else could review it as well.

Reviewed-by: Niklas Cassel <cassel@kernel.org>

Dear Niklas,

Thank you very much for your review and suggestions. Let's wait for 
others' opinions.

Best regards,
Hans