[PATCH v2 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528
From: Yao Zi <hidden>
Date: 2025-05-09 00:43:32
Also in:
linux-devicetree, linux-phy, linux-rockchip, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB 3.0 controllers. Describe it and the pipe-phy grf which it depends on. Signed-off-by: Yao Zi <redacted> --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 193b84b5e912..672350400774 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi@@ -334,6 +334,11 @@ vpu_grf: syscon@ff340000 { reg = <0x0 0xff340000 0x0 0x8000>; }; + pipe_phy_grf: syscon@ff348000 { + compatible = "rockchip,rk3528-pipe-phy-grf", "syscon"; + reg = <0x0 0xff348000 0x0 0x8000>; + }; + vo_grf: syscon@ff360000 { compatible = "rockchip,rk3528-vo-grf", "syscon"; reg = <0x0 0xff360000 0x0 0x10000>;
@@ -778,6 +783,23 @@ dmac: dma-controller@ffd60000 { arm,pl330-periph-burst; }; + combphy: phy@ffdc0000 { + compatible = "rockchip,rk3528-naneng-combphy"; + reg = <0x0 0xffdc0000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, + <&cru PCLK_PIPE_GRF>; + clock-names = "ref", "apb", + "pipe"; + assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PCIE_PIPE_PHY>, <&cru SRST_P_PCIE_PHY>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&vpu_grf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3528-pinctrl"; rockchip,grf = <&ioc_grf>;
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2.49.0