Re: [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support
From: Yao Zi <hidden>
Date: 2025-05-08 23:13:44
Also in:
linux-devicetree, linux-phy, linux-rockchip, lkml
On Thu, May 08, 2025 at 07:26:13PM +0200, Heiko Stuebner wrote:
Am Donnerstag, 8. Mai 2025, 15:53:06 Mitteleuropäische Sommerzeit schrieb Yao Zi:quoted
Rockchip RK3528 integrates one naneng-combphy that is able to operate in PCIe and USB3 mode. The control logic is similar to previous variants of naneng-combphy but the register layout is apperantly different from the RK3568 one. Signed-off-by: Yao Zi <redacted> --- .../rockchip/phy-rockchip-naneng-combphy.c | 180 +++++++++++++++++- 1 file changed, 179 insertions(+), 1 deletion(-)diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 1d1c7723584b..7c92f7ac3c7f 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c@@ -20,7 +20,40 @@ #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) -/* COMBO PHY REG */ +/* RK3528 COMBO PHY REG */ +#define RK3528_PHYREG6 0x18 +#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10) +#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2 +#define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4) +#define RK3528_PHYREG6_SSC_UPWARD 0 +#define RK3528_PHYREG6_SSC_DOWNWARD 1 +#define RK3528_PHYREG40 0x100 +#define RK3528_PHYREG40_SSC_EN BIT(20) +#define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0) +#define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d +#define RK3528_PHYREG42 0x108 +#define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29) +#define RK3528_PHYREG42_CKDRV_CLK_PLL 0 +#define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1 +#define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7) +#define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9 +#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4) +#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7 +#define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0) +#define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0 +#define RK3528_PHYREG80 0x200 +#define RK3528_PHYREG80_CTLE_EN BIT(17) +#define RK3528_PHYREG81 0x204 +#define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5) +#define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0) +#define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7 +#define RK3528_PHYREG83 0x20c +#define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0) +#define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6 +#define RK3528_PHYREG86 0x218 +#define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14)I'd think staying with one layout would be best, so not doing this indentation here. Instead maybe follow the other ones like
Though seems more clear, it's reasonable to keep the style consistent. Will change it in v2, thanks.
#define RK3528_PHYREG6 0x18 #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10) #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2 #define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4) #define RK3528_PHYREG6_SSC_UPWARD 0 #define RK3528_PHYREG6_SSC_DOWNWARD 1 #define RK3528_PHYREG40 0x100 #define RK3528_PHYREG40_SSC_EN BIT(20) #define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0) #define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d ... i.e. register + bits + blank line other than that Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Best regards, Yao Zi