On Mon, 2025-03-24 at 17:59 +0000, Willie Thai wrote:
quoted hunk ↗ jump to hunk
Add EMMCG5 enum to compatible list of pinctrl binding for emmc
enabling.
Cc: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Willie Thai <redacted>
---
.../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 1
+
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
pinctrl.yaml
b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
pinctrl.yaml
index 80974c46f3ef..cb75e979f5e0 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-
pinctrl.yaml
@@ -276,6 +276,7 @@ additionalProperties:
- BMCINT
- EMMCG1
- EMMCG4
+ - EMMCG5
What pin configuration does this correspond to for the eMMC controller?
These groups aren't arbitrary, they correspond to the 1, 4 and 8-bit
bus modes.
You may have added this squash a warning, but I suspect the pinctrl
configuration in your devicetree is incorrect.
Andrew
- EMMCG8
- ESPI
- ESPIALT