On Wed, 05 Mar 2025 05:38:22 +0000,
Peter Chen [off-list ref] wrote:

+	pmu-a520 {
+		compatible = "arm,cortex-a520-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
+	};
+
+	pmu-a720 {
+		compatible = "arm,cortex-a720-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
+	};
+
+	pmu-spe {
+		compatible = "arm,statistical-profiling-extension-v1";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
+	};

SPE should follow the same model as the PMU, as each CPU has its own
SPE implementation, exposing different micro-architectural details.

The rest looks OK.

	M.

-- 
Without deviation from the norm, progress is not possible.