[PATCH 2/3] arm64: dts: rockchip: Add I2C controllers for RK3528
From: Yao Zi <hidden>
Date: 2025-03-09 07:06:49
Also in:
linux-devicetree, linux-i2c, linux-rockchip, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
Describe I2C controllers shipped by RK3528 in devicetree. Signed-off-by: Yao Zi <redacted> --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 104 +++++++++++++++++++++++ 1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 04ca2e2b3e9b..860b6057e5c2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi@@ -19,6 +19,14 @@ / { #size-cells = <2>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2;
@@ -466,6 +474,102 @@ uart7: serial@ffa28000 { status = "disabled"; }; + i2c0: i2c@ffa50000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa50000 0x0 0x1000>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ffa58000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa58000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ffa60000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa60000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ffa68000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa68000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffa70000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa70000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ffa78000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa78000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@ffa80000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@ffa88000 { + compatible = "rockchip,rk3528-i2c", + "rockchip,rk3399-i2c"; + reg = <0x0 0xffa88000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + saradc: adc@ffae0000 { compatible = "rockchip,rk3528-saradc"; reg = <0x0 0xffae0000 0x0 0x10000>;
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