Re: [PATCH v2 2/7] clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2025-03-06 14:19:13
Also in:
linux-clk, linux-devicetree, linux-pm, linux-renesas-soc, lkml
On Thu, 27 Feb 2025 at 13:25, John Madieu [off-list ref] wrote:
Add required clocks and resets signals for the TSU IP available on the Renesas RZ/G3E SoC Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.15.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
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