Re: [PATCH v2 1/7] dt-bindings: npu: rockchip,rknn: Add bindings
From: Rob Herring <robh@kernel.org>
Date: 2025-02-25 16:02:51
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dri-devel, linux-devicetree, linux-doc, linux-media, linux-rockchip, lkml
On Tue, Feb 25, 2025 at 08:55:47AM +0100, Tomeu Vizoso wrote:
quoted hunk ↗ jump to hunk
Add the bindings for the Neural Processing Unit IP from Rockchip. v2: - Adapt to new node structure (one node per core, each with its own IOMMU) - Several misc. fixes from Sebastian Reichel Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Signed-off-by: Sebastian Reichel <redacted> --- .../bindings/npu/rockchip,rknn-core.yaml | 152 +++++++++++++++++++++ 1 file changed, 152 insertions(+)diff --git a/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e8d0afe4a7d1c4f166cf13a9f4aa7c1901362a3f --- /dev/null +++ b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml@@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/npu/rockchip,rknn-core.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Neural Processing Unit IP from Rockchip + +maintainers: + - Tomeu Vizoso <tomeu@tomeuvizoso.net> + +description: + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's + open source NVDLA IP. + +properties: + $nodename: + pattern: '^npu-core@[a-f0-9]+$' + + compatible: + oneOf: + - items: + - enum: + - rockchip,rk3588-rknn-core-top + - const: rockchip,rknn-core-top
Drop the fallbacks unless you have some evidence that the IP is the same across a lot of SoCs. If you don't, then rockchip,rk3588-rknn-core-top can be the fallback whenever there are more compatible SoCs. Or if there's version/feature registers that otherwise make it discoverable, then a common compatible is fine.
+ - items: + - enum: + - rockchip,rk3588-rknn-core + - const: rockchip,rknn-core
I don't understand the difference between core and core-top. That needs to be explained in the top-level description.
+ + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 4 + + clock-names: + items: + - const: aclk + - const: hclk + - const: npu + - const: pclk + minItems: 2 + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + npu-supply: true + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: srst_a + - const: srst_h + + sram-supply: true
Group supply properties together
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - iommus
+ - npu-supply
+ - power-domains
+ - resets
+ - reset-names
+ - sram-supply
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rknn-core-top
+ then:
+ properties:
+ clocks:
+ minItems: 4
+
+ clock-names:
+ minItems: 4
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rknn-core
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rknn_core_top: npu-core@fdab0000 {npu@...
+ compatible = "rockchip,rk3588-rknn-core-top", "rockchip,rknn-core-top";
+ reg = <0x0 0xfdab0000 0x0 0x9000>;
+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+ assigned-clock-rates = <200000000>;
+ clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
+ <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "aclk", "hclk", "npu", "pclk";
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&rknn_mmu_top>;
+ npu-supply = <&vdd_npu_s0>;
+ power-domains = <&power RK3588_PD_NPUTOP>;
+ resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
+ reset-names = "srst_a", "srst_h";
+ sram-supply = <&vdd_npu_mem_s0>;
+ };
+
+ rknn_core_1: npu-core@fdac0000 {
+ compatible = "rockchip,rk3588-rknn-core", "rockchip,rknn-core";
+ reg = <0x0 0xfdac0000 0x0 0x9000>;
+ clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
+ clock-names = "aclk", "hclk";
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&rknn_mmu_1>;
+ npu-supply = <&vdd_npu_s0>;
+ power-domains = <&power RK3588_PD_NPU1>;
+ resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>;
+ reset-names = "srst_a", "srst_h";
+ sram-supply = <&vdd_npu_mem_s0>;
+ };
+ };
+...
--
2.48.1