Hi Krzysztof,

-----Original Message-----
From: Alim Akhtar <alim.akhtar@samsung.com>
Sent: 05 February 2025 21:41
To: 'Krzysztof Kozlowski' <krzk@kernel.org>; 'Sudeep Holla'
[off-list ref]
Cc: 'Devang Tailor' <redacted>; robh@kernel.org;
krzk+dt@kernel.org; conor+dt@kernel.org; devicetree@vger.kernel.org; linux-
arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
kernel@vger.kernel.org; faraz.ata@samsung.com
Subject: RE: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-
v920

Hi Krzysztof

quoted

-----Original Message-----
From: Krzysztof Kozlowski <krzk@kernel.org>
Sent: Wednesday, February 5, 2025 9:22 PM
To: Sudeep Holla <redacted>; Alim Akhtar
[off-list ref]
Cc: 'Devang Tailor' <redacted>; robh@kernel.org;
krzk+dt@kernel.org; conor+dt@kernel.org; devicetree@vger.kernel.org;
linux-arm-kernel@lists.infradead.org;
linux-samsung-soc@vger.kernel.org;
linux-kernel@vger.kernel.org; faraz.ata@samsung.com
Subject: Re: [PATCH v2] arm64: dts: add cpu cache information to
ExynosAuto-v920

On 31/01/2025 14:27, Sudeep Holla wrote:

quoted

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[snip]
 > +		l3_cache_cl0: l3-cache0 {
You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and
Remove the specific node for CL1, because both are same.

What do you mean by "both are same" ?
Do you mean both have exact same properties but are physically
different caches ? OR Do you mean it is just one shared cache ?

If former, we still need distinct node to get the cacheinfo about
shareability correct. If this is about avoiding duplication of
errors, you can probably define some macro and avoid it, but we need
2 nodes in the devicetree.

If latter, you suggestion is correct.

No answers here, so I drop this patch from my queue.

It took sometime to get the confirmation internally (because of new year
holiday) Just replied to Sudeep. It will be great if you can consider this patch
for this cycle.
Thanks!

Is there anything else need to be done for this patch or do you suggest me to re-send this patch again?

quoted

Best regards,
Krzysztof