Re: [PATCH] arm64: errata: Add Ampere erratum AC04_CPU_50 workaround alternative

On Tue, 04 Feb 2025 21:46:06 +0000,
Zaid Alali [off-list ref] wrote:

On Tue, Jan 28, 2025 at 08:34:47AM +0000, Marc Zyngier wrote:

quoted

On Mon, 27 Jan 2025 20:18:29 +0000,
Zaid Alali [off-list ref] wrote:

quoted

Add an alternative code sequence to work around Ampere erratum
AC03_CPU_50 on AmpereOne and Ampere1A.

Due to AC03_CPU_50, when ICC_PMR_EL1 should have a value of 0xf0 a
direct read of the register will return a value of 0xf8. An incorrect
value from a direct read can only happen with the value 0xf0.

Under which precise conditions? Does it equally apply to virtual
interrupts or SCR_EL3.FIQ==0, for which there is no non-secure shift
(which I can only assume is the source of the erratum)? Does it
equally affect G0 and G1 interrupts?

Hi Marc,

This only occurs when:
When SCR_EL3.FIQ==1 and PE is NOT in EL3/Secure State,
and ICC_PMR_EL1.Priority==LowestPriorityImplemented==0xf8 (highest priority is 0x00).
 
Does it equally apply to virtual interrupts or SCR_EL3.FIQ==0?
 
Based on this Defect (AArch-21735) and our implementation, it only 
affected ICC_PMR_EL1, therefore does not apply to virtual interrupts.

Are you saying that this is erratum is *strictly* AARCH-21735?

	M.

-- 
Without deviation from the norm, progress is not possible.