[PATCH 3/9] arm64: dts: apple: t7001: Add cpufreq nodes
From: Nick Chan <hidden>
Date: 2024-12-22 17:53:35
Also in:
asahi, linux-devicetree, lkml
Subsystem:
arm/apple machine support, the rest · Maintainers:
Sven Peter, Janne Grunau, Linus Torvalds
Add the cpufreq nodes for Apple A8X SoC. Signed-off-by: Nick Chan <redacted> --- arch/arm64/boot/dts/apple/t7001.dtsi | 52 ++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi
index a76e034c85e3..15fd91d12f30 100644
--- a/arch/arm64/boot/dts/apple/t7001.dtsi
+++ b/arch/arm64/boot/dts/apple/t7001.dtsi@@ -35,6 +35,8 @@ cpu0: cpu@0 { compatible = "apple,typhoon"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; };
@@ -43,6 +45,8 @@ cpu1: cpu@1 { compatible = "apple,typhoon"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; };
@@ -51,11 +55,53 @@ cpu2: cpu@2 { compatible = "apple,typhoon"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; }; + typhoon_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <300>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <49000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <31000>; + }; + opp04 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <4>; + clock-latency-ns = <32000>; + }; + opp05 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <5>; + clock-latency-ns = <32000>; + }; + opp06 { + opp-hz = /bits/ 64 <1392000000>; + opp-level = <6>; + clock-latency-ns = <37000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <7>; + clock-latency-ns = <41000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;
@@ -63,6 +109,12 @@ soc { nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>;
--
2.47.1