[PATCH 3/3] arm64: cpufeature: workaround AmpereOne FEAT_BBM level 2
From: Yang Shi <hidden>
Date: 2024-11-18 18:17:45
Also in:
lkml
Subsystem:
arm64 port (aarch64 architecture), the rest · Maintainers:
Catalin Marinas, Will Deacon, Linus Torvalds
FEAT_BBM level 2 is not advertised on AmpereOne because of a bug when collapsing stage 2 mappings from smaller to larger translations. That doesn't impact splitting stage 1 mappings (whether stage 2 is enabled or not), so workaround it by detecting CPUID. Signed-off-by: Yang Shi <redacted> --- arch/arm64/include/asm/cpufeature.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index c7ca5f9f88bb..d9b20eb43d31 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h@@ -847,10 +847,19 @@ static inline bool bbmlv2_available(void) { u64 mmfr2; u32 bbm; + static const struct midr_range ampereone[] = { + MIDR_ALL_VERSIONS(MIDR_AMPERE1), + MIDR_ALL_VERSIONS(MIDR_AMPERE1A), + {} + }; mmfr2 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); bbm = cpuid_feature_extract_unsigned_field(mmfr2, ID_AA64MMFR2_EL1_BBM_SHIFT); - return bbm == ID_AA64MMFR2_EL1_BBM_2; + if ((bbm == ID_AA64MMFR2_EL1_BBM_2) || + is_midr_in_range_list(read_cpuid_id(), ampereone)) + return true; + + return false; } int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
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2.41.0