Re: [PATCH v3 07/12] clk: rp1: Add support for clocks provided by RP1
From: Andrea della Porta <andrea.porta@suse.com>
Date: 2024-11-05 08:30:13
Also in:
linux-clk, linux-devicetree, linux-gpio, linux-pci, lkml
Hi Stephen, On 15:20 Mon 28 Oct , Stephen Boyd wrote:
Quoting Andrea della Porta (2024-10-28 07:07:24)quoted
diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c new file mode 100644 index 000000000000..69b9cf037cb2 --- /dev/null[...]quoted
+ +struct rp1_clockman { + struct device *dev; + void __iomem *regs;Do you still need this if there's a regmap?
Unfortunately the clk_divider registered in rp1_register_pll_divider() mandates the use of a MMIO registeri, and yes, the divider and teh other clock shares some registers. AFAICT there were attempts to upstream generic regmap support for clk_divider, but right now there are just custom implementations (e.g. drivers/clk/qcom/clk-regmap.c). So, in order to use regmap, that clock divider shoulf be first augmented with regmap support. Please let me know if you think it's worth the effort.
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+ struct regmap *regmap; + spinlock_t regs_lock; /* spinlock for all clocks */Do you need this or is the spinlock in the regmap sufficient?
The original code wrapped multiple registers write/read inside the spinlock, so I suspect that using the internal regmap spinlock for each single transaciton (so to open up for interleaved register access, although I have no evidence of that) could have side-effects so I would prefer to stay safe and manage the lock from outside. I could easily use regmap_multi_reg_write() and friends to synchronize access across multiple registers but then we would have the problem above about missing regmap support in clk_divider, since now it's solved by passing the same spinlock to it too. I'm open to alternatives here...
quoted
+ + /* Must be last */ + struct clk_hw_onecell_data onecell; +}; + +struct rp1_pll_core_data { + const char *name;These 'name' members can move to clk_init_data?
You've read my mind, I was exactly planning that for the next revision
quoted
+ u32 cs_reg; + u32 pwr_reg; + u32 fbdiv_int_reg; + u32 fbdiv_frac_reg; + unsigned long flags;And probably flags as well? It seems like clk_init_data should be declared at the same time as struct rp1_pll_core_data is.
Ditto.
quoted
+ u32 fc0_src; +}; + +struct rp1_pll_data { + const char *name; + u32 ctrl_reg; + unsigned long flags; + u32 fc0_src; +}; + +struct rp1_pll_ph_data { + const char *name; + unsigned int phase; + unsigned int fixed_divider; + u32 ph_reg; + unsigned long flags; + u32 fc0_src; +}; + +struct rp1_pll_divider_data { + const char *name; + u32 sec_reg; + unsigned long flags; + u32 fc0_src; +}; + +struct rp1_clock_data { + const char *name; + int num_std_parents; + int num_aux_parents; + unsigned long flags; + u32 oe_mask; + u32 clk_src_mask; + u32 ctrl_reg; + u32 div_int_reg; + u32 div_frac_reg; + u32 sel_reg; + u32 div_int_max; + unsigned long max_freq; + u32 fc0_src; +}; + +struct rp1_clk_desc { + struct clk_hw *(*clk_register)(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc); + const void *data; + struct clk_hw hw; + struct rp1_clockman *clockman; + unsigned long cached_rate; + struct clk_divider div; +}; + +#define FIELD_SET(_reg, _mask, _val) \ +do { \ + u32 mask = (_mask); \ + (_reg) &= ~mask; \ + (_reg) |= FIELD_PREP(mask, (_val)); \Please just write reg &= ~mask reg |= FIELD_PREP(mask, val); instead of using this macro.
Ack.
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+} while (0) + +[...]quoted
+ +static struct clk_hw *rp1_register_pll_core(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + const struct rp1_pll_core_data *pll_core_data = desc->data; + struct clk_init_data init = { }; + int ret; + + /* All of the PLL cores derive from the external oscillator. */ + init.parent_data = desc->hw.init->parent_data; + init.num_parents = desc->hw.init->num_parents; + init.name = pll_core_data->name; + init.ops = &rp1_pll_core_ops; + init.flags = pll_core_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL; + + desc->clockman = clockman; + desc->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &desc->hw); + + if (ret) + return ERR_PTR(ret); + + return &desc->hw; +} + +static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + const struct rp1_pll_data *pll_data = desc->data; + struct clk_init_data init = { }; + int ret; + + init.parent_data = desc->hw.init->parent_data; + init.num_parents = desc->hw.init->num_parents; + init.name = pll_data->name; + init.ops = &rp1_pll_ops; + init.flags = pll_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL; + + desc->clockman = clockman; + desc->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &desc->hw); + + if (ret) + return ERR_PTR(ret); + + return &desc->hw; +} + +static struct clk_hw *rp1_register_pll_ph(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + const struct rp1_pll_ph_data *ph_data = desc->data; + struct clk_init_data init = { }; + int ret; + + init.parent_data = desc->hw.init->parent_data; + init.num_parents = desc->hw.init->num_parents; + init.name = ph_data->name; + init.ops = &rp1_pll_ph_ops; + init.flags = ph_data->flags | CLK_IGNORE_UNUSED; + + desc->clockman = clockman; + desc->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &desc->hw); + + if (ret) + return ERR_PTR(ret); + + return &desc->hw; +} + +static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + const struct rp1_pll_data *divider_data = desc->data; + struct clk_init_data init = { }; + int ret; + + init.parent_data = desc->hw.init->parent_data; + init.num_parents = desc->hw.init->num_parents; + init.name = divider_data->name; + init.ops = &rp1_pll_divider_ops; + init.flags = divider_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL; + + desc->div.reg = clockman->regs + divider_data->ctrl_reg;Why is 'regs' used here? Isn't everything using a regmap now so it's all offsets?
Already explained above.
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+ desc->div.shift = PLL_SEC_DIV_SHIFT; + desc->div.width = PLL_SEC_DIV_WIDTH; + desc->div.flags = CLK_DIVIDER_ROUND_CLOSEST; + desc->div.flags |= CLK_IS_CRITICAL; + desc->div.lock = &clockman->regs_lock; + desc->div.hw.init = &init; + desc->div.table = pll_sec_div_table; + + desc->clockman = clockman; + + ret = devm_clk_hw_register(clockman->dev, &desc->div.hw); + + if (ret) + return ERR_PTR(ret); + + return &desc->div.hw; +} + +static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, + struct rp1_clk_desc *desc) +{ + const struct rp1_clock_data *clock_data = desc->data; + struct clk_init_data init = { }; + int ret; + + if (WARN_ON_ONCE(MAX_CLK_PARENTS < + clock_data->num_std_parents + clock_data->num_aux_parents)) + return NULL; + + /* There must be a gap for the AUX selector */ + if (WARN_ON_ONCE(clock_data->num_std_parents > AUX_SEL && + desc->hw.init->parent_data[AUX_SEL].index != -1)) + return NULL; + + init.parent_data = desc->hw.init->parent_data; + init.num_parents = desc->hw.init->num_parents; + init.name = clock_data->name; + init.flags = clock_data->flags | CLK_IGNORE_UNUSED; + init.ops = &rp1_clk_ops; + + desc->clockman = clockman; + desc->hw.init = &init; + + ret = devm_clk_hw_register(clockman->dev, &desc->hw); + + if (ret) + return ERR_PTR(ret); + + return &desc->hw; +} + +/* Assignment helper macros for different clock types. */ +#define _REGISTER(f, ...) { .clk_register = f, __VA_ARGS__ } + +#define PARENT_CLK(pnum, ...) .hw.init = &(const struct clk_init_data) { \Instead of this macro just use CLK_HW_INIT_HW() or CLK_HW_INIT_PARENTS_DATA()?
Ack.
quoted
+ .parent_data = (const struct \ + clk_parent_data[]) { \ + __VA_ARGS__ \ + }, \ + .num_parents = pnum } + +#define CLK_DATA(type, ...) .data = &(struct type) { __VA_ARGS__ } + +#define REGISTER_PLL_CORE(...) _REGISTER(&rp1_register_pll_core, \ + __VA_ARGS__) + +#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \ + __VA_ARGS__) + +#define REGISTER_PLL_PH(...) _REGISTER(&rp1_register_pll_ph, \ + __VA_ARGS__) + +#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ + __VA_ARGS__) + +#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \ + __VA_ARGS__) + +static struct rp1_clk_desc clk_desc_array[] = { + [RP1_PLL_SYS_CORE] = REGISTER_PLL_CORE(PARENT_CLK(1, { .index = 0 }), + CLK_DATA(rp1_pll_core_data, + .name = "pll_sys_core", + .cs_reg = PLL_SYS_CS, + .pwr_reg = PLL_SYS_PWR, + .fbdiv_int_reg = PLL_SYS_FBDIV_INT, + .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, + )), + + [RP1_PLL_AUDIO_CORE] = REGISTER_PLL_CORE(PARENT_CLK(1, { .index = 0 }), + CLK_DATA(rp1_pll_core_data, + .name = "pll_audio_core", + .cs_reg = PLL_AUDIO_CS, + .pwr_reg = PLL_AUDIO_PWR, + .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, + .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, + )), + + [RP1_PLL_VIDEO_CORE] = REGISTER_PLL_CORE(PARENT_CLK(1, { .index = 0 }), + CLK_DATA(rp1_pll_core_data, + .name = "pll_video_core", + .cs_reg = PLL_VIDEO_CS, + .pwr_reg = PLL_VIDEO_PWR, + .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, + .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, + )), + + [RP1_PLL_SYS] = REGISTER_PLL(PARENT_CLK(1, + { .hw = &clk_desc_array[RP1_PLL_SYS_CORE].hw } + ), + CLK_DATA(rp1_pll_data, + .name = "pll_sys", + .ctrl_reg = PLL_SYS_PRIM, + .fc0_src = FC_NUM(0, 2), + )), + + [RP1_CLK_ETH_TSU] = REGISTER_CLK(PARENT_CLK(1, { .index = 0 }), + CLK_DATA(rp1_clock_data, + .name = "clk_eth_tsu", + .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_ETH_TSU_CTRL, + .div_int_reg = CLK_ETH_TSU_DIV_INT, + .sel_reg = CLK_ETH_TSU_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 7), + )), + + [RP1_CLK_SYS] = REGISTER_CLK(PARENT_CLK(3, + { .index = 0 }, + { .index = -1 }, + { .hw = &clk_desc_array[RP1_PLL_SYS].hw } + ), + CLK_DATA(rp1_clock_data, + .name = "clk_sys", + .num_std_parents = 3, + .num_aux_parents = 0, + .ctrl_reg = CLK_SYS_CTRL, + .div_int_reg = CLK_SYS_DIV_INT, + .sel_reg = CLK_SYS_SEL, + .div_int_max = DIV_INT_24BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 4), + .clk_src_mask = 0x3, + )), + + [RP1_PLL_SYS_PRI_PH] = REGISTER_PLL_PH(PARENT_CLK(1, + { .hw = &clk_desc_array[RP1_PLL_SYS].hw } + ), + CLK_DATA(rp1_pll_ph_data, + .name = "pll_sys_pri_ph", + .ph_reg = PLL_SYS_PRIM, + .fixed_divider = 2, + .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(1, 2), + )), + + [RP1_PLL_SYS_SEC] = REGISTER_PLL_DIV(PARENT_CLK(1, + { .hw = &clk_desc_array[RP1_PLL_SYS_CORE].hw } + ), + CLK_DATA(rp1_pll_data, + .name = "pll_sys_sec", + .ctrl_reg = PLL_SYS_SEC, + .fc0_src = FC_NUM(2, 2), + )), +}; + +static const struct regmap_range rp1_reg_ranges[] = { + regmap_reg_range(PLL_SYS_CS, PLL_SYS_SEC), + regmap_reg_range(PLL_AUDIO_CS, PLL_AUDIO_TERN), + regmap_reg_range(PLL_VIDEO_CS, PLL_VIDEO_SEC), + regmap_reg_range(GPCLK_OE_CTRL, GPCLK_OE_CTRL), + regmap_reg_range(CLK_SYS_CTRL, CLK_SYS_DIV_INT), + regmap_reg_range(CLK_SYS_SEL, CLK_SYS_SEL), + regmap_reg_range(CLK_SLOW_SYS_CTRL, CLK_SLOW_SYS_DIV_INT), + regmap_reg_range(CLK_SLOW_SYS_SEL, CLK_SLOW_SYS_SEL), + regmap_reg_range(CLK_DMA_CTRL, CLK_DMA_DIV_INT), + regmap_reg_range(CLK_DMA_SEL, CLK_DMA_SEL), + regmap_reg_range(CLK_UART_CTRL, CLK_UART_DIV_INT), + regmap_reg_range(CLK_UART_SEL, CLK_UART_SEL), + regmap_reg_range(CLK_ETH_CTRL, CLK_ETH_DIV_INT), + regmap_reg_range(CLK_ETH_SEL, CLK_ETH_SEL), + regmap_reg_range(CLK_PWM0_CTRL, CLK_PWM0_SEL), + regmap_reg_range(CLK_PWM1_CTRL, CLK_PWM1_SEL), + regmap_reg_range(CLK_AUDIO_IN_CTRL, CLK_AUDIO_IN_DIV_INT), + regmap_reg_range(CLK_AUDIO_IN_SEL, CLK_AUDIO_IN_SEL), + regmap_reg_range(CLK_AUDIO_OUT_CTRL, CLK_AUDIO_OUT_DIV_INT), + regmap_reg_range(CLK_AUDIO_OUT_SEL, CLK_AUDIO_OUT_SEL), + regmap_reg_range(CLK_I2S_CTRL, CLK_I2S_DIV_INT), + regmap_reg_range(CLK_I2S_SEL, CLK_I2S_SEL), + regmap_reg_range(CLK_MIPI0_CFG_CTRL, CLK_MIPI0_CFG_DIV_INT), + regmap_reg_range(CLK_MIPI0_CFG_SEL, CLK_MIPI0_CFG_SEL), + regmap_reg_range(CLK_MIPI1_CFG_CTRL, CLK_MIPI1_CFG_DIV_INT), + regmap_reg_range(CLK_MIPI1_CFG_SEL, CLK_MIPI1_CFG_SEL), + regmap_reg_range(CLK_PCIE_AUX_CTRL, CLK_PCIE_AUX_DIV_INT), + regmap_reg_range(CLK_PCIE_AUX_SEL, CLK_PCIE_AUX_SEL), + regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, CLK_USBH0_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH0_MICROFRAME_SEL, CLK_USBH0_MICROFRAME_SEL), + regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, CLK_USBH1_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH1_MICROFRAME_SEL, CLK_USBH1_MICROFRAME_SEL), + regmap_reg_range(CLK_USBH0_SUSPEND_CTRL, CLK_USBH0_SUSPEND_DIV_INT), + regmap_reg_range(CLK_USBH0_SUSPEND_SEL, CLK_USBH0_SUSPEND_SEL), + regmap_reg_range(CLK_USBH1_SUSPEND_CTRL, CLK_USBH1_SUSPEND_DIV_INT), + regmap_reg_range(CLK_USBH1_SUSPEND_SEL, CLK_USBH1_SUSPEND_SEL), + regmap_reg_range(CLK_ETH_TSU_CTRL, CLK_ETH_TSU_DIV_INT), + regmap_reg_range(CLK_ETH_TSU_SEL, CLK_ETH_TSU_SEL), + regmap_reg_range(CLK_ADC_CTRL, CLK_ADC_DIV_INT), + regmap_reg_range(CLK_ADC_SEL, CLK_ADC_SEL), + regmap_reg_range(CLK_SDIO_TIMER_CTRL, CLK_SDIO_TIMER_DIV_INT), + regmap_reg_range(CLK_SDIO_TIMER_SEL, CLK_SDIO_TIMER_SEL), + regmap_reg_range(CLK_SDIO_ALT_SRC_CTRL, CLK_SDIO_ALT_SRC_DIV_INT), + regmap_reg_range(CLK_SDIO_ALT_SRC_SEL, CLK_SDIO_ALT_SRC_SEL), + regmap_reg_range(CLK_GP0_CTRL, CLK_GP0_SEL), + regmap_reg_range(CLK_GP1_CTRL, CLK_GP1_SEL), + regmap_reg_range(CLK_GP2_CTRL, CLK_GP2_SEL), + regmap_reg_range(CLK_GP3_CTRL, CLK_GP3_SEL), + regmap_reg_range(CLK_GP4_CTRL, CLK_GP4_SEL), + regmap_reg_range(CLK_GP5_CTRL, CLK_GP5_SEL), + regmap_reg_range(CLK_SYS_RESUS_CTRL, CLK_SYS_RESUS_CTRL), + regmap_reg_range(CLK_SLOW_SYS_RESUS_CTRL, CLK_SLOW_SYS_RESUS_CTRL), + regmap_reg_range(FC0_REF_KHZ, FC0_RESULT), + regmap_reg_range(VIDEO_CLK_VEC_CTRL, VIDEO_CLK_VEC_DIV_INT), + regmap_reg_range(VIDEO_CLK_VEC_SEL, VIDEO_CLK_DPI_DIV_INT), + regmap_reg_range(VIDEO_CLK_DPI_SEL, VIDEO_CLK_MIPI1_DPI_SEL), +}; + +static const struct regmap_access_table rp1_reg_table = { + .yes_ranges = rp1_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(rp1_reg_ranges), +}; + +static const struct regmap_config rp1_clk_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = PLL_VIDEO_SEC, + .name = "rp1-clk", + .rd_table = &rp1_reg_table, +}; + +static int rp1_clk_probe(struct platform_device *pdev) +{ + const size_t asize = ARRAY_SIZE(clk_desc_array); + struct rp1_clk_desc *desc; + struct device *dev = &pdev->dev; + struct rp1_clockman *clockman; + struct clk_hw **hws; + unsigned int i; + + clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize), + GFP_KERNEL); + if (!clockman) + return -ENOMEM; + + spin_lock_init(&clockman->regs_lock); + clockman->dev = dev; + + clockman->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clockman->regs)) + return PTR_ERR(clockman->regs); + + clockman->regmap = devm_regmap_init_mmio(dev, clockman->regs, + &rp1_clk_regmap_cfg); + if (IS_ERR(clockman->regmap)) { + dev_err(dev, "could not init clock regmap\n");return dev_err_probe()?
Ack. Many thanks, Andrea
quoted
+ return PTR_ERR(clockman->regmap); + } + + clockman->onecell.num = asize; + hws = clockman->onecell.hws; + + for (i = 0; i < asize; i++) { + desc = &clk_desc_array[i]; + if (desc->clk_register && desc->data) { + hws[i] = desc->clk_register(clockman, desc); + if (IS_ERR_OR_NULL(hws[i])) + dev_err_probe(dev, PTR_ERR(hws[i]), + "Unable to register clock: %s\n", + clk_hw_get_name(hws[i])); + } + } + + platform_set_drvdata(pdev, clockman); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &clockman->onecell); +}