On 2024-09-05 11:30, Uwe Kleine-König wrote:

1 second long pulses with a period size of 1 second, so a constant high
signal?

Hi, I think I was unclear. The SoC documentation is not that detailed. 
But I think I understand how it works now.

One register contains the minimum duration (d_min). And then there is 
one 8 bit register for the signal low period (lp) and then another 8bit 
register for the high period (hp). Per my understanding a change of 
polarity is then just a swap of lp and hp.

The period is d_min * (lp + hp) and duty_cycle (on time) is then 
d_min*hp (per my understanding of the linux api). This means that there 
can be different settings that result in the same pwm signal (if you 
double d_min and halving lp and hp the signal should be the same).

This means that when requesting a period and duty cycle you need to 
search through the configuration space to find the optimal value.

Another thing that would be interesting is, if it can happen that you
get a mixed signal. That is, if you update from

	.period = A
	.duty_cycle = B

to

	.period = C
	.duty_cycle = D

that you get one period with length C and duty_cycle B when the period
completes after configuring period but before duty_cycle.

Best regards
UWe

I will perform this test also.

MvH

Benjamin Larsson