Hi.

On 26/08/2024 19:07, Conor Dooley wrote:

To clarify the hw architecture we are discussing about 3 memory regions:

quoted

- chip_scu: <0x1fa20000 0x384>
- scu: <0x1fb00020 0x94c>

                   ^
I'm highly suspicious of a register region that begins at 0x20. What is
at 0x1fb00000?

Unknown, no documentation of those registers.

quoted

- gpio: <0x1fbf0200 0xbc>

Do you have a link to the register map documentation for this hardware?

There is no public documentation, what is available is the current 
driver source and this (less useful) partial map here:

https://github.com/gchmiel/en7512_kernel5/blob/master/linux-5-new/arch/mips/include/asm/tc3162/tc3162.h#L860

Registers with FMAP and FLAP are parts of the PWM functionality.

quoted

The memory regions above are used by the following IC blocks:
- clock: chip_scu and scu

What is the differentiation between these two different regions? Do they
provide different clocks? Are registers from both of them required in
order to provide particular clocks?

chip-scu contains the registers the clock driver handles. But scu has 
registers with the word clock in the description but both regions does 
not seem to be needed for a specific clock.

chip-scu contains pinctrl, iomux and clocks

scu contains random bits and functional muxes for serdes

quoted

- pinctrl (io-muxing/gpio_chip/irq_chip): chip_scu and gpio

Ditto here. Are these actually two different sets of iomuxes, or are
registers from both required to mux a particular pin?

io-muxes for pins are done in chip-scu, pwm muxing is done in the gpio 
register range together with chip-scu (ensure there are no conflicts).

MvH

Benjamin Larsson