Re: [PATCH 3/3] clk: at91: clk-sam9x60-pll: increase maximum amount of plls
From: claudiu beznea <claudiu.beznea@tuxon.dev>
Date: 2024-08-31 13:27:21
Also in:
linux-clk, lkml
On 29.08.2024 19:42, Ryan.Wanner@microchip.com wrote:
quoted hunk ↗ jump to hunk
From: Ryan Wanner <Ryan.Wanner@microchip.com> Increase maximum amount of PLLs to 9 to support SAMA7D65 SoC PLL requirements. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> --- drivers/clk/at91/clk-sam9x60-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index fda041102224..cefd9948e103 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c@@ -23,7 +23,7 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) -#define PLL_MAX_ID 7 +#define PLL_MAX_ID 9
This patch need to go before SAMA7D65 clock driver.
struct sam9x60_pll_core {
struct regmap *regmap;