On Wed, Aug 28, 2024 at 05:37:07PM +0800, lijiang wrote:

On Wed, Aug 28, 2024 at 6:48 AM Baoquan He [off-list ref] wrote:

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On 08/27/24 at 01:24pm, Will Deacon wrote:

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On Mon, Aug 26, 2024 at 02:52:02PM +0800, Kuan-Ying Lee wrote:

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Since arm64 supports 5-level page tables, we need to add this
information to vmcoreinfo to make debug tools know if 5-level
page table is enabled or not.

Missing this information will break the debug tool like crash [1].

Sorry, the above line was mistakenly expressed.

Currently, the crash tool doesn't support 4K page with 5-level
page tables (LPA2), so I initially planned to add this
information to implement support for 4K page with 5-level page
table in the crash tool.

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[1] https://github.com/crash-utility/crash

Signed-off-by: Kuan-Ying Lee <redacted>
---
 Documentation/admin-guide/kdump/vmcoreinfo.rst | 6 ++++++
 arch/arm64/kernel/vmcore_info.c                | 3 +++
 2 files changed, 9 insertions(+)

In which case, wouldn't you also want to know about pgtable_l4_enabled()?

That is a good question. I guess it's deduced in code, mostly needed for
different PAGE_OFFSET, how to transfer virtual addr to physical addr,
etc.

Thanks for the information, Baoquan.

If I understand correctly, for arm64, currently, the crash tool determines
the levels of the page table based on page size and va_bits, and then
decides how to translate the address, such as calculating it in conjunction
with other values, e.g: kernel pgd, offset, etc.

Thanks for the information. I will then try to use VA_BITS to determine
if it is a 5-level page table.
Let me investigate further.

Thanks,
Kuan-Ying Lee

For more details, please refer to this one:
https://github.com/crash-utility/crash/blob/master/arm64.c


Thanks
Lianbo

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Add Crash utility experts here.