Re: [PATCH v2 08/10] arm64: dts: exynos: Add initial support for exynos8895 SoC
From: Rob Herring <robh@kernel.org>
Date: 2024-08-13 17:48:14
Also in:
linux-devicetree, linux-gpio, linux-samsung-soc, lkml
On Wed, Aug 07, 2024 at 12:08:56PM +0300, Ivaylo Ivanov wrote:
quoted hunk ↗ jump to hunk
Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu 15 Plus (m1891). Add minimal support for that SoC, including: - All 8 cores via PSCI - ChipID - Generic ARMV8 Timer - Enumarate all pinctrl nodes Further platform support will be added over time. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++ arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++ 2 files changed, 1631 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsidiff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi new file mode 100644 index 000000000..1dcb61e2e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi@@ -0,0 +1,1378 @@ +// SPDX-License-Identifier: BSD-3-Clause
Every other Exynos dts file is GPL2. This should match or do dual licensing which is preferred.
+/*
+ * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2024, Ivaylo Ivanov [off-list ref]
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa1: gpa1 {gpio-1
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa2: gpa2 {gpio-2
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa4: gpa4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ bt_hostwake: bt-hostwake {Name pinctrl nodes with some pattern to distinguish what they are. '-pins$' is a common pattern. Looking at the binding patch, you may need to split it out since we were probably stuck with no pattern on existing chips.
+ samsung,pins = "gpa2-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + };