Re: [PATCH v4 4/6] ata: ahci_imx: Add 32bits DMA limit for i.MX8QM AHCI SATA

On Thu, Aug 08, 2024 at 12:35:01AM +0200, Niklas Cassel wrote:

On Fri, Aug 02, 2024 at 02:30:45AM +0000, Hongxing Zhu wrote:

quoted

quoted

Does this solve your problem:

diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 581704e61f28..fc86e2c8c42b 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c

@@ -747,12 +747,11 @@ int ahci_platform_init_host(struct platform_device

*pdev,
                        ap->ops = &ata_dummy_port_ops;
        }

-       if (hpriv->cap & HOST_CAP_64) {
-               rc = dma_coerce_mask_and_coherent(dev,
DMA_BIT_MASK(64));
-               if (rc) {
-                       dev_err(dev, "Failed to enable 64-bit DMA.\n");
-                       return rc;
-               }
+       rc = dma_coerce_mask_and_coherent(dev,
+                       DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 :
32));
+       if (rc) {
+               dev_err(dev, "DMA enable failed\n");
+               return rc;
        }

        rc = ahci_reset_controller(host);

Hi Niklas:
I'm so sorry to reply late.
About the 32bit DMA limitation of i.MX8QM AHCI SATA.
It's seems that one "dma-ranges" property in the DT can let i.MX8QM SATA
 works fine in my past days tests without this commit.
How about drop these driver changes, and add "dma-ranges" for i.MX8QM SATA?
Thanks a lot for your kindly help.

Hello Richard,

did you try my suggested patch above?


If you look at dma-ranges:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#dma-ranges

"dma-ranges" property should be used on a bus device node
(such as PCI host bridges).

Yes, 32bit is limited by internal bus farbic, not AHCI controller.

It look like
hsio-bus
{
	dma-ranges = <low 4G space>
	sata@addr
	{
		...
	}
}

This should be correct reflect hardware behavior.  force ahci to 32bit dma
mask should be a wordaround.

Frank

It does not seem correct to add this property (describing the DMA limit
of the AHCI controller, a PCI endpoint) on the PCI host bridge/controller.

This property belongs to the AHCI controller, not the upstream PCI
host bridge/controller.

AHCI has a specific register to describe if the hardware can support
64-bit DMA addresses or not, so if my suggested patch works for you,
it seems like a more elegant solution (which also avoids having to
abuse device tree properties).


Kind regards,
Niklas