Re: [PATCH] arm64/sysreg: Correct the values for GICv4.1
From: Zenghui Yu <yuzenghui@huawei.com>
Date: 2024-07-21 09:30:11
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On 2024/7/19 5:55, Raghavendra Rao Ananta wrote:
quoted hunk ↗ jump to hunk
Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM. Hence, correct them to reflect ARM ARM. Signed-off-by: Raghavendra Rao Ananta <redacted> --- arch/arm64/tools/sysreg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a4c1dd4741a47..7ceaa1e0b4bc2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg@@ -149,7 +149,7 @@ Res0 63:32 UnsignedEnum 31:28 GIC 0b0000 NI 0b0001 GICv3 - 0b0010 GICv4p1 + 0b0011 GICv4p1 EndEnum UnsignedEnum 27:24 Virt_frac 0b0000 NI@@ -903,7 +903,7 @@ EndEnum UnsignedEnum 27:24 GIC 0b0000 NI 0b0001 IMP - 0b0010 V4P1 + 0b0011 V4P1 EndEnum SignedEnum 23:20 AdvSIMD 0b0000 IMP
Fortunately there is no user for this bit inside kernel. We had checked against the correct hard-coded value (0x3) in gic_cpuif_has_vsgi(). Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>