Re: [PATCH v2 7/9] arm64: dts: rockchip: use generic Ethernet PHY reset bindings for Lunzn Fastrhino R68S
From: Heiko Stübner <heiko@sntech.de>
Date: 2024-07-04 19:12:15
Also in:
linux-devicetree, linux-rockchip, lkml
Hi, Am Sonntag, 30. Juni 2024, 17:00:08 CEST schrieb Chukun Pan:
quoted hunk ↗ jump to hunk
Replace the deprecated snps,reset-xxx bindings to the generic Ethernet PHY reset GPIO bindings. Also updates the delays based on the vendor recommendations. Fixes: b9f8ca655d80 ("arm64: dts: rockchip: Add Lunzn Fastrhino R68S") Signed-off-by: Chukun Pan <redacted> --- .../boot/dts/rockchip/rk3568-fastrhino-r68s.dts | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-)diff --git a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts index ce2a5e1ccefc..02d966d218fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts@@ -39,10 +39,6 @@ &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk &gmac0_rgmii_bus>; - snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 15ms, 50ms for rtl8211f */ - snps,reset-delays-us = <0 15000 50000>; tx_delay = <0x3c>; rx_delay = <0x2f>; status = "okay";@@ -61,10 +57,6 @@ &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_rgmii_bus>; - snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 15ms, 50ms for rtl8211f */ - snps,reset-delays-us = <0 15000 50000>; tx_delay = <0x4f>; rx_delay = <0x26>; status = "okay";@@ -76,6 +68,9 @@ rgmii_phy0: ethernet-phy@1 { reg = <0x1>; pinctrl-0 = <ð_phy0_reset_pin>; pinctrl-names = "default"; + reset-assert-us = <20000>; + reset-deassert-us = <100000>;
what's the reason behind the changed timings? The original comment stated, /* Reset time is 15ms, 50ms for rtl8211f */ so that timing change needs an explanation please :-) Thanks Heiko
quoted hunk ↗ jump to hunk
+ reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; }; };@@ -85,6 +80,9 @@ rgmii_phy1: ethernet-phy@1 { reg = <0x1>; pinctrl-0 = <ð_phy1_reset_pin>; pinctrl-names = "default"; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; }; };