Re: [PATCH v1 5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller
From: Samuel Holland <samuel.holland@sifive.com>
Date: 2024-02-18 15:33:22
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Hi Krzysztof, On 2024-02-17 3:12 AM, Krzysztof Kozlowski wrote:
On 16/02/2024 01:08, Samuel Holland wrote:quoted
From: Eric Lin <redacted> Add YAML DT binding documentation for the SiFive Private L2 Cache controller. Some functionality and the corresponding register bits were removed in the sifive,pl2cache1 version of the hardware, which creates the unusual situation where the newer hardware's compatible string is the fallback for the older one. Signed-off-by: Eric Lin <redacted> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> --- Changes in v1: - Add back select: clause to binding - Make sifive,pl2cache1 the fallback for sifive,pl2cache0 - Fix the order of the reg property declaration - Document the sifive,perfmon-counters propertyThis is no v1. Please implement entire feedback from previous v2, v3 or whatever it was and reference old posting or continue the numbering.
The old posting is referenced in the cover letter: This series is a follow-up to Eric Lin's series "[PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver": https://lore.kernel.org/linux-riscv/20230720135125.21240-1-eric.lin@sifive.com/ (local) So these changes include implementation of the feedback from that v2. Regards, Samuel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel