[PATCH v7 1/6] dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible
From: Peng Fan (OSS) <hidden>
Date: 2024-02-18 06:48:09
Also in:
linux-devicetree, lkml
Subsystem:
mailbox api, open firmware and flattened device tree bindings, the rest · Maintainers:
Jassi Brar, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
From: Peng Fan <peng.fan@nxp.com> Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible string. And the MUs in AONMIX has internal RAMs for SCMI shared buffer usage. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- .../devicetree/bindings/mailbox/fsl,mu.yaml | 58 +++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
index 12e7a7d536a3..00631afcd51d 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml@@ -29,8 +29,11 @@ properties: - const: fsl,imx8ulp-mu - const: fsl,imx8-mu-scu - const: fsl,imx8-mu-seco - - const: fsl,imx93-mu-s4 - const: fsl,imx8ulp-mu-s4 + - const: fsl,imx93-mu-s4 + - const: fsl,imx95-mu + - const: fsl,imx95-mu-ele + - const: fsl,imx95-mu-v2x - items: - const: fsl,imx93-mu - const: fsl,imx8ulp-mu
@@ -95,6 +98,19 @@ properties: power-domains: maxItems: 1 + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "^sram@[a-f0-9]+": + $ref: /schemas/sram/sram.yaml# + unevaluatedProperties: false + required: - compatible - reg
@@ -122,6 +138,15 @@ allOf: required: - interrupt-names + - if: + not: + properties: + compatible: + const: fsl,imx95-mu + then: + patternProperties: + "^sram@[a-f0-9]+": false + additionalProperties: false examples:
@@ -134,3 +159,34 @@ examples: interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x10000>; + ranges; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + };
--
2.37.1
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