RE: [EXT] Re: [PATCH v12 7/7] phy: freescale: Add HDMI PHY driver for i.MX8MQ
From: Sandor Yu <hidden>
Date: 2024-02-04 14:29:05
Also in:
dri-devel, linux-devicetree, linux-phy, lkml
Hi Alexander, Thanks your comments,
-----Original Message----- From: Alexander Stein <redacted> Sent: 2024年1月17日 17:47 To: dmitry.baryshkov@linaro.org; andrzej.hajda@intel.com; neil.armstrong@linaro.org; Laurent Pinchart [off-list ref]; jonas@kwiboo.se; jernej.skrabec@gmail.com; airlied@gmail.com; daniel@ffwll.ch; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; shawnguo@kernel.org; s.hauer@pengutronix.de; festevam@gmail.com; vkoul@kernel.org; dri-devel@lists.freedesktop.org; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-phy@lists.infradead.org; Sandor Yu [off-list ref] Cc: kernel@pengutronix.de; dl-linux-imx <redacted>; Sandor Yu [off-list ref]; Oliver Brown [off-list ref]; sam@ravnborg.org Subject: [EXT] Re: [PATCH v12 7/7] phy: freescale: Add HDMI PHY driver for i.MX8MQ Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button Hi Sandor, thanks for the update. Am Mittwoch, 10. Januar 2024, 02:08:48 CET schrieb Sandor Yu:quoted
Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ. Cadence HDP-TX PHY could be put in either DP mode or HDMI mode baseonquoted
the configuration chosen. HDMI PHY mode is configurated in the driver. Signed-off-by: Sandor Yu <redacted> Tested-by: Alexander Stein <redacted> --- v11->v12: - Adjust clk disable order. - Return error code to replace -1 for function wait_for_ack(). - Use bool for variable pclk_in. - Add year 2024 to copyright. drivers/phy/freescale/Kconfig | 10 + drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c | 959 ++++++++++++++++++++ 3 files changed, 970 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdmi.cdiff --git a/drivers/phy/freescale/Kconfigb/drivers/phy/freescale/Kconfig index c39709fd700ac..14f47b7cc77ab 100644--- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig@@ -45,6 +45,16 @@ config PHY_FSL_IMX8MQ_DP Enable this to support the Cadence HDPTX DP PHY driver on i.MX8MQ SOC. +config PHY_FSL_IMX8MQ_HDMI + tristate "Freescale i.MX8MQ HDMI PHY support" + depends on OF && HAS_IOMEM + depends on COMMON_CLK + select GENERIC_PHY + select CDNS_MHDP_HELPER + help + Enable this to support the Cadence HDPTX HDMI PHY driver + on i.MX8MQ SOC. + endif config PHY_FSL_LYNX_28Gdiff --git a/drivers/phy/freescale/Makefileb/drivers/phy/freescale/Makefile index 47e5285209fa8..1380ac31c2ead 100644--- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile@@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_FSL_IMX8MQ_DP) +=phy-fsl-imx8mq-dp.oquoted
+obj-$(CONFIG_PHY_FSL_IMX8MQ_HDMI) += phy-fsl-imx8mq-hdmi.o obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.odiff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.cb/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c new file mode 100644 index 0000000000000..9e03c726f290c--- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c@@ -0,0 +1,959 @@[snip] +int cdns_hdptx_hdmi_phy_valid(struct phy *phy, enum phy_mode mode, +int submode, + union phy_configure_opts*opts) This function can be made static.
OK, thanks! B.R Sandor
Thanks and best regards, Alexanderquoted
+{ + u32 rate = opts->hdmi.pixel_clk_rate; + int i; + + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++) + if (rate ==pixel_clk_output_ctrl_table[i].pixel_clk_freq_min)quoted
+ return 0; + + return -EINVAL; +} + +static int cdns_hdptx_hdmi_phy_init(struct phy *phy) { + return 0; +} + +static int cdns_hdptx_hdmi_configure(struct phy *phy, + union phy_configure_opts *opts){quoted
+ struct cdns_hdptx_hdmi_phy *cdns_phy = phy_get_drvdata(phy); + int ret; + + cdns_phy->pixel_clk_rate = opts->hdmi.pixel_clk_rate; + cdns_phy->color_space = opts->hdmi.color_space; + cdns_phy->bpc = opts->hdmi.bpc; + + /* Check HDMI FW alive before HDMI PHY init */ + ret = hdptx_phy_check_alive(cdns_phy); + if (!ret) { + dev_err(cdns_phy->dev, "NO HDMI FW running\n"); + return -ENXIO; + } + + /* Configure PHY */ + if (hdptx_hdmi_phy_cfg(cdns_phy, cdns_phy->pixel_clk_rate) < 0) { + dev_err(cdns_phy->dev, "failed to set phy pclock\n"); + return -EINVAL; + } + + ret = hdptx_hdmi_phy_power_up(cdns_phy); + if (ret < 0) + return ret; + + hdptx_hdmi_phy_set_vswing(cdns_phy); + + return 0; +} + +static const struct phy_ops cdns_hdptx_hdmi_phy_ops = { + .init = cdns_hdptx_hdmi_phy_init, + .configure = cdns_hdptx_hdmi_configure, + .power_on = cdns_hdptx_hdmi_phy_on, + .power_off = cdns_hdptx_hdmi_phy_off, + .validate = cdns_hdptx_hdmi_phy_valid, + .owner = THIS_MODULE, +}; + +static int cdns_hdptx_hdmi_phy_probe(struct platform_device *pdev) { + struct cdns_hdptx_hdmi_phy *cdns_phy; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct phy_provider *phy_provider; + struct resource *res; + struct phy *phy; + int ret; + + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); + if (!cdns_phy) + return -ENOMEM; + + dev_set_drvdata(dev, cdns_phy); + cdns_phy->dev = dev; + mutex_init(&cdns_phy->mbox_mutex); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res)); + if (IS_ERR(cdns_phy->regs)) + return PTR_ERR(cdns_phy->regs); + + phy = devm_phy_create(dev, node, &cdns_hdptx_hdmi_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy->attrs.mode = PHY_MODE_HDMI; + + cdns_phy->phy = phy; + phy_set_drvdata(phy, cdns_phy); + + /* init base struct for access mhdp mailbox */ + cdns_phy->base.dev = cdns_phy->dev; + cdns_phy->base.regs = cdns_phy->regs; + cdns_phy->base.mbox_mutex = &cdns_phy->mbox_mutex; + + ret = hdptx_hdmi_clk_enable(cdns_phy); + if (ret) { + dev_err(dev, "Init clk fail\n"); + return -EINVAL; + } + + phy_provider = devm_of_phy_provider_register(dev,of_phy_simple_xlate);quoted
+ if (IS_ERR(phy_provider)) { + ret = PTR_ERR(phy_provider); + goto clk_disable; + } + + dev_dbg(dev, "probe success!\n"); + + return 0; + +clk_disable: + hdptx_hdmi_clk_disable(cdns_phy); + + return -EINVAL; +} + +static int cdns_hdptx_hdmi_phy_remove(struct platform_device *pdev) { + struct cdns_hdptx_hdmi_phy *cdns_phy = +platform_get_drvdata(pdev); + + hdptx_hdmi_clk_disable(cdns_phy); + + return 0; +} + +static const struct of_device_id cdns_hdptx_hdmi_phy_of_match[] = { + {.compatible = "fsl,imx8mq-hdmi-phy" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, cdns_hdptx_hdmi_phy_of_match); + +static struct platform_driver cdns_hdptx_hdmi_phy_driver = { + .probe = cdns_hdptx_hdmi_phy_probe, + .remove = cdns_hdptx_hdmi_phy_remove, + .driver = { + .name = "cdns-hdptx-hdmi-phy", + .of_match_table = cdns_hdptx_hdmi_phy_of_match, + } +}; +module_platform_driver(cdns_hdptx_hdmi_phy_driver); + +MODULE_AUTHOR("Sandor Yu [off-list ref]"); +MODULE_DESCRIPTION("Cadence HDP-TX HDMI PHY driver"); +MODULE_LICENSE("GPL");-- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider http://www.tq-/ group.com%2F&data=05%7C02%7CSandor.yu%40nxp.com%7Cb17a4addce1e4 8b54f8a08dc17414379%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 %7C638410816282055456%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA wMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7 C%7C&sdata=YFO2ShpepVs%2B%2FTSDfzLdZjkPc7s0VHrqjX9jxsqSXok%3D&res erved=0
_______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel