On 1/30/2024 8:42 PM, Suzuki K Poulose wrote:

On 30/01/2024 09:02, Tao Zhang wrote:

quoted

CMB_TIER register is CMB subunit timestamp insertion enable register.
Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp
following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit.
Set this bit to 1 to request a timestamp following a CMB CTI timestamp
request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp
for all packets.

Reviewed-by: James Clark <redacted>
Signed-off-by: Tao Zhang <redacted>
Signed-off-by: Jinlong Mao <redacted>
---
  .../testing/sysfs-bus-coresight-devices-tpdm  |  35 +++++
  drivers/hwtracing/coresight/coresight-tpdm.c  | 121 +++++++++++++++++-
  drivers/hwtracing/coresight/coresight-tpdm.h  |  31 +++++
  3 files changed, 180 insertions(+), 7 deletions(-)

diff --git 

a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm 
b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
index b6cf050861ed..e8c76ce4dd15 100644

--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm

@@ -214,3 +214,38 @@ KernelVersion    6.9

  Contact:    Jinlong Mao (QUIC) [off-list ref], Tao 
Zhang (QUIC) [off-list ref]
  Description:
          (RW) Set/Get the mask of the pattern for the CMB subunit TPDM.
+
+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts
+Date:        January 2024
+KernelVersion    6.9
+Contact:    Jinlong Mao (QUIC) [off-list ref], Tao Zhang 
(QUIC) [off-list ref]
+Description:
+        (Write) Set the pattern timestamp of CMB tpdm. Read
+        the pattern timestamp of CMB tpdm.
+
+        Accepts only one of the 2 values -  0 or 1.
+        0 : Disable CMB pattern timestamp.
+        1 : Enable CMB pattern timestamp.
+
+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts
+Date:        January 2024
+KernelVersion    6.9
+Contact:    Jinlong Mao (QUIC) [off-list ref], Tao Zhang 
(QUIC) [off-list ref]
+Description:
+        (RW) Set/Get the trigger timestamp of the CMB for tpdm.
+
+        Accepts only one of the 2 values -  0 or 1.
+        0 : Set the CMB trigger type to false
+        1 : Set the CMB trigger type to true
+
+What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all
+Date:        January 2024
+KernelVersion    6.9
+Contact:    Jinlong Mao (QUIC) [off-list ref], Tao Zhang 
(QUIC) [off-list ref]
+Description:
+        (RW) Read or write the status of timestamp upon all interface.
+        Only value 0 and 1  can be written to this node. Set this 
node to 1 to requeset
+        timestamp to all trace packet.
+        Accepts only one of the 2 values -  0 or 1.
+        0 : Disable the timestamp of all trace packets.
+        1 : Enable the timestamp of all trace packets.

diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c 

b/drivers/hwtracing/coresight/coresight-tpdm.c
index 07587287d9fa..22966d541230 100644

--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c

@@ -322,6 +322,31 @@ static void tpdm_enable_dsb(struct tpdm_drvdata 

*drvdata)
      writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
  }
  +static void set_cmb_tier(struct tpdm_drvdata *drvdata)
+{
+    u32 val;
+
+    val = readl_relaxed(drvdata->base + TPDM_CMB_TIER);
+
+    /* Clear all relevant fields */
+    val &= ~(TPDM_CMB_TIER_PATT_TSENAB | TPDM_CMB_TIER_TS_ALL |
+         TPDM_CMB_TIER_XTRIG_TSENAB);
+
+    /* Set pattern timestamp type and enablement */
+    if (drvdata->cmb->patt_ts)
+        val |= TPDM_CMB_TIER_PATT_TSENAB;
+
+    /* Set trigger timestamp */
+    if (drvdata->cmb->trig_ts)
+        val |= TPDM_CMB_TIER_XTRIG_TSENAB;
+
+    /* Set all timestamp enablement*/
+    if (drvdata->cmb->ts_all)
+        val |= TPDM_CMB_TIER_TS_ALL;
+
+    writel_relaxed(val, drvdata->base + TPDM_CMB_TIER);
+}
+
  static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)
  {
      u32 val, i;

@@ -341,6 +366,8 @@ static void tpdm_enable_cmb(struct tpdm_drvdata 

*drvdata)
              drvdata->base + TPDM_CMB_XPMR(i));
      }
  +    set_cmb_tier(drvdata);
+
      val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
      /*
       * Set to 0 for continuous CMB collection mode,

@@ -687,9 +714,18 @@ static ssize_t enable_ts_show(struct device *dev,

                    char *buf)
  {
      struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+    struct tpdm_dataset_attribute *tpdm_attr =
+        container_of(attr, struct tpdm_dataset_attribute, attr);
+    ssize_t size = -EINVAL;
  -    return sysfs_emit(buf, "%u\n",
-             (unsigned int)drvdata->dsb->patt_ts);
+    if (tpdm_attr->mem == DSB_PATT)
+        size = sysfs_emit(buf, "%u\n",
+                  (unsigned int)drvdata->dsb->patt_ts);
+    else if (tpdm_attr->mem == CMB_PATT)
+        size = sysfs_emit(buf, "%u\n",
+                  (unsigned int)drvdata->cmb->patt_ts);
+
+    return size;
  }
    /*

@@ -701,17 +737,23 @@ static ssize_t enable_ts_store(struct device *dev,

                     size_t size)
  {
      struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+    struct tpdm_dataset_attribute *tpdm_attr =
+        container_of(attr, struct tpdm_dataset_attribute, attr);
      unsigned long val;
        if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
          return -EINVAL;
  -    spin_lock(&drvdata->spinlock);
-    drvdata->dsb->patt_ts = !!val;
-    spin_unlock(&drvdata->spinlock);
+    guard(spinlock)(&drvdata->spinlock);
+    if (tpdm_attr->mem == DSB_PATT)
+        drvdata->dsb->patt_ts = !!val;
+    else if (tpdm_attr->mem == CMB_PATT)
+        drvdata->cmb->patt_ts = !!val;
+    else
+        return -EINVAL;
+
      return size;
  }
-static DEVICE_ATTR_RW(enable_ts);
    static ssize_t set_type_show(struct device *dev,
                   struct device_attribute *attr,

@@ -842,6 +884,68 @@ static ssize_t cmb_mode_store(struct device *dev,

  }
  static DEVICE_ATTR_RW(cmb_mode);
  +static ssize_t cmb_ts_all_show(struct device *dev,
+                   struct device_attribute *attr,
+                   char *buf)
+{
+    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+    return sysfs_emit(buf, "%u\n",
+              (unsigned int)drvdata->cmb->ts_all);
+}
+
+static ssize_t cmb_ts_all_store(struct device *dev,
+                struct device_attribute *attr,
+                const char *buf,
+                size_t size)
+{
+    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+    unsigned long val;
+
+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
+        return -EINVAL;
+
+    guard(spinlock)(&drvdata->spinlock);
+    if (val)
+        drvdata->cmb->ts_all = true;
+    else
+        drvdata->cmb->ts_all = false;
+
+    return size;
+}
+static DEVICE_ATTR_RW(cmb_ts_all);
+
+static ssize_t cmb_trig_ts_show(struct device *dev,
+                struct device_attribute *attr,
+                char *buf)
+{
+    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+    return sysfs_emit(buf, "%u\n",
+              (unsigned int)drvdata->cmb->trig_ts);
+}
+
+static ssize_t cmb_trig_ts_store(struct device *dev,
+                 struct device_attribute *attr,
+                 const char *buf,
+                 size_t size)
+{
+    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+    unsigned long val;
+
+    if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
+        return -EINVAL;
+
+    guard(spinlock)(&drvdata->spinlock);
+    if (val)
+        drvdata->cmb->trig_ts = true;
+    else
+        drvdata->cmb->trig_ts = false;
+
+    return size;
+}
+static DEVICE_ATTR_RW(cmb_trig_ts);
+
  static struct attribute *tpdm_dsb_edge_attrs[] = {
      &dev_attr_ctrl_idx.attr,
      &dev_attr_ctrl_val.attr,

@@ -910,7 +1014,7 @@ static struct attribute *tpdm_dsb_patt_attrs[] = {

      DSB_PATT_MASK_ATTR(5),
      DSB_PATT_MASK_ATTR(6),
      DSB_PATT_MASK_ATTR(7),
-    &dev_attr_enable_ts.attr,
+    DSB_PATT_ENABLE_TS,
      &dev_attr_set_type.attr,
      NULL,
  };

@@ -964,6 +1068,7 @@ static struct attribute *tpdm_cmb_patt_attrs[] = {

      CMB_PATT_ATTR(1),
      CMB_PATT_MASK_ATTR(0),
      CMB_PATT_MASK_ATTR(1),
+    CMB_PATT_ENABLE_TS,
      NULL,
  };
  @@ -976,6 +1081,8 @@ static struct attribute *tpdm_dsb_attrs[] = {
    static struct attribute *tpdm_cmb_attrs[] = {
      &dev_attr_cmb_mode.attr,
+    &dev_attr_cmb_ts_all.attr,
+    &dev_attr_cmb_trig_ts.attr,
      NULL,
  };
  diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h 
b/drivers/hwtracing/coresight/coresight-tpdm.h
index 8cb8a9b35384..725a35e5893f 100644

--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h

@@ -11,6 +11,8 @@

    /* CMB Subunit Registers */
  #define TPDM_CMB_CR        (0xA00)
+/*CMB subunit timestamp insertion enable register*/

    ^^ Minor nit: Same as previous patch.          ^^

Sure, I will update this to the next patch series.


Best,

Tao

Suzuki

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