[PATCH v2 2/2] clk: mediatek: add infracfg reset controller for mt7988
From: Frank Wunderlich <hidden>
Date: 2024-01-05 16:30:13
Also in:
linux-clk, linux-devicetree, linux-mediatek, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: Frank Wunderlich <redacted> Infracfg can also operate as reset controller, add support for it. Signed-off-by: Frank Wunderlich <redacted> --- drivers/clk/mediatek/clk-mt7988-infracfg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
index 8011ef278bea..1660a45349ff 100644
--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c@@ -14,6 +14,9 @@ #include "clk-gate.h" #include "clk-mux.h" #include <dt-bindings/clock/mediatek,mt7988-clk.h> +#include <dt-bindings/reset/mediatek,mt7988-resets.h> + +#define INFRA_RST_SET_OFFSET 0x80 static DEFINE_SPINLOCK(mt7988_clk_lock);
@@ -249,12 +252,29 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), }; +static u16 infra_rst_ofs[] = { + INFRA_RST_SET_OFFSET, +}; + +static u16 infra_idx_map[] = { + [MT7988_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 9, +}; + +static struct mtk_clk_rst_desc infra_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), + .rst_idx_map = infra_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), +}; + static const struct mtk_clk_desc infra_desc = { .clks = infra_clks, .num_clks = ARRAY_SIZE(infra_clks), .mux_clks = infra_muxes, .num_mux_clks = ARRAY_SIZE(infra_muxes), .clk_lock = &mt7988_clk_lock, + .rst_desc = &infra_rst_desc, }; static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
--
2.34.1
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