RE: [PATCH v7 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver

Hi Bjorn/ Lorenzo/Krzysztof,

Can you please provide any update on this patch series.

Regards,
Thippeswamy H

-----Original Message-----
From: Bjorn Helgaas <helgaas@kernel.org>
Sent: Wednesday, September 6, 2023 10:55 PM
To: Havalige, Thippeswamy <redacted>
Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
bhelgaas@google.com; krzysztof.kozlowski+dt@linaro.org;
devicetree@vger.kernel.org; linux-pci@vger.kernel.org; lpieralisi@kernel.org;
robh@kernel.org; conor+dt@kernel.org; Simek, Michal
[off-list ref]; Gogada, Bharat Kumar
[off-list ref]
Subject: Re: [PATCH v7 3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver

On Wed, Aug 30, 2023 at 02:37:07PM +0530, Thippeswamy Havalige wrote:

quoted

Add support for Xilinx XDMA Soft IP core as Root Port.

The Zynq UltraScale+ MPSoCs devices support XDMA soft IP module in
programmable logic.

The integrated XDMA soft IP block has integrated bridge function that
can act as PCIe Root Port.

quoted

+	if (!pci_is_root_bus(bus)) {
+		/* Checking whether the link is up is the last line of
+		 * defense, and this check is inherently racy by definition.
+		 * Sending a PIO request to a downstream device when the

link is

quoted

+		 * down causes an unrecoverable error, and a reset of the

entire

quoted

+		 * PCIe controller will be needed. We can reduce the

likelihood

quoted

+		 * of that unrecoverable error by checking whether the link is
+		 * up, but we can't completely prevent it because the link may
+		 * go down between the link-up check and the PIO request.
+		 */

Looks fine to me.  If Lorenzo or Krzysztof thinks this is ready to go, maybe they
will tidy the comment above, i.e.,

  /*
   * Checking whether ...

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