Re: [PATCH v4 18/36] arm64/gcs: Context switch GCS state for EL0
From: Catalin Marinas <catalin.marinas@arm.com>
Date: 2023-08-11 15:32:21
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On Mon, Aug 07, 2023 at 11:00:23PM +0100, Mark Brown wrote:
quoted hunk ↗ jump to hunk
@@ -271,12 +272,31 @@ static void flush_tagged_addr_state(void) clear_thread_flag(TIF_TAGGED_ADDR); } +#ifdef CONFIG_ARM64_GCS + +static void flush_gcs(void) +{ + if (system_supports_gcs()) {
Nitpick: use "if (system_supports_gcs()) return" when we have more than a line in the conditional block (slightly more consistent with other places).
quoted hunk ↗ jump to hunk
+ gcs_free(current); + current->thread.gcs_el0_mode = 0; + write_sysreg_s(0, SYS_GCSCRE0_EL1); + write_sysreg_s(0, SYS_GCSPR_EL0); + } +}
Do we need and isb() or there's one on this path? If it's only EL0 making use of this register, we should be fine with the ERET before returning to user. Not sure whether the kernel uses this, GCSSTTR doesn't need it.
quoted hunk ↗ jump to hunk
+static void gcs_thread_switch(struct task_struct *next) +{ + if (!system_supports_gcs()) + return; + + gcs_preserve_current_state(); + + /* + * Ensure that GCS changes are observable by/from other PEs in + * case of migration. + */ + if (task_gcs_el0_enabled(current) || task_gcs_el0_enabled(next)) + gcsb_dsync();
What's this barrier for? The spec (at least the version I have) only talks about accesses, nothing to do with the registers that we context switch here. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel