Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver

Hello Jerome,

On Thu, Jun 08, 2023 at 10:53:31AM +0200, Jerome Brunet wrote:

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+
+static struct clk_regmap s4_fclk_div4 = {
+     .data = &(struct clk_regmap_gate_data){
+             .offset = ANACTRL_FIXPLL_CTRL1,
+             .bit_idx = 21,
+     },
+     .hw.init = &(struct clk_init_data){
+             .name = "fclk_div4",
+             /*
+              * For more information, please refer to s4_fixed_pll_dco.
+              */

While div2 and div3 got an explanation from previous SoCs, they others -
like div4/div7/etc ... - have been able to cope with rw ops so far.
Why is the S4 different for all these clocks ?

The chip was changed fixed pll for security reasons.

Fixed PLL registers are not writable in the kernel phase. Write of fixed
PLL-related register will cause the system to crash.

That is definitely worth mentionning

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Requiring RO ops (or fishy clock flags) is usually a sign that a clock
is used without an appropriate driver.

Neil is currently dealing with the dt-bindings, please
* Adjust your patchset accordingly
* Wait for his v2 to land, you'll need it.

I saw Neil patch series with merging 'private' and 'public' clock
bindings parts. Should I send the same patchset for a1 clocks after v6.5
landed?

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+             .ops = &clk_regmap_gate_ro_ops,
+             .parent_hws = (const struct clk_hw *[]) {
+                     &s4_fclk_div4_div.hw
+             },
+             .num_parents = 1,
+     },
+};
+

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-- 
Thank you,
Dmitry

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