[PATCH v3] meson saradc: fix clock divider mask length
flat view
STALE1234d
LANDED
From: George Stark <hidden>
Date: 2023-06-06 16:55:10
Also in:
linux-amlogic, linux-iio, lkml
Subsystem:
iio subsystem and drivers, the rest · Maintainers:
Jonathan Cameron, Linus Torvalds
Landed in mainline as c57fa0037024 on 2023-06-10.
According to datasheets of supported meson SOCs length of ADC_CLK_DIV
field is 6 bits long. Although all supported SOCs have the register
with that field documented later SOCs use external clock rather than
ADC internal clock so this patch affects only meson8 family (S8* SOCs)
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: George Stark <redacted>
---
Changelog:
v1 -> v2:
* Update commit message
v2 -> v3:
* Update commit message
---
drivers/iio/adc/meson_saradc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 85b6826cc10c..b93ff42b8c19 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c@@ -72,7 +72,7 @@ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
--
2.38.4
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