Re: [PATCH 01/32] perf: Allow a PMU to have a parent

On Tue, Jun 06, 2023 at 02:06:24PM +0100, Mark Rutland wrote:

On Thu, Apr 06, 2023 at 09:49:38PM +0200, Peter Zijlstra wrote:

quoted

On Thu, Apr 06, 2023 at 05:44:45PM +0100, Jonathan Cameron wrote:

quoted

On Thu, 6 Apr 2023 14:40:40 +0200
Peter Zijlstra [off-list ref] wrote:

quoted

On Thu, Apr 06, 2023 at 11:16:07AM +0100, Jonathan Cameron wrote:

quoted

In the long run I agree it would be good.  Short term there are more instances of
struct pmu that don't have parents than those that do (even after this series).
We need to figure out what to do about those before adding checks on it being
set.  

Right, I don't think you've touched *any* of the x86 PMUs for example,
and getting everybody that boots an x86 kernel a warning isn't going to
go over well :-)

It was tempting :) "Warning: Parentless PMU: try a different architecture."

Haha!

quoted

I'd love some inputs on what the x86 PMU devices parents should be?
CPU counters in general tend to just spin out of deep in the architecture code.

For the 'simple' ones I suppose we can use the CPU device.

Uh, *which* CPU device? Do we have a container device for all CPUs?

drivers/base/cpu.c:per_cpu(cpu_sys_devices, cpu) for whatever the core
pmu is for that cpu ?

quoted

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My overall favorite is an l2 cache related PMU that is spun up in
arch/arm/kernel/irq.c init_IRQ()

That's an artifact of the L2 cache controller driver getting initialized there;
ideally we'd have a device for the L2 cache itself (which presumably should
hang off an aggregate CPU device).

/sys/devices/system/cpu/cpuN/cache/indexM

has a struct device somewhere in
drivers/base/cacheinfo.c:ci_index_dev or somesuch.

quoted

Yeah, we're going to have a ton of them as well. Some of them are PCI
devices and have a clear parent, others, not so much :/

In a number of places the only thing we have is the PMU driver, and we don't
have a driver (or device) for the HW block it's a part of. Largely that's
interconnect PMUs; we could create container devices there.

Dont they have a PCI device? But yeah, some are going to be a wee bit
challenging.

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