[PATCH v6 10/19] clk: mediatek: Add MT8188 mfgcfg clock support
From: Garmin.Chang <hidden>
Date: 2023-03-09 14:17:59
Also in:
linux-mediatek
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
Add MT8188 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Garmin.Chang <redacted> --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8188-mfg.c | 47 +++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e05fcc2769fa..dfe2c74c422c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile@@ -94,7 +94,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \ clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \ clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \ - clk-mt8188-ipe.o + clk-mt8188-ipe.o clk-mt8188-mfg.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c b/drivers/clk/mediatek/clk-mt8188-mfg.c
new file mode 100644
index 000000000000..a9a54ca7bbd1
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-mfg.c@@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2022 MediaTek Inc. +// Author: Garmin Chang <garmin.chang@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include <dt-bindings/clock/mediatek,mt8188-clk.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs mfgcfg_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) + +static const struct mtk_gate mfgcfg_clks[] = { + GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "mfg_ck_fast_ref", 0), +}; + +static const struct mtk_clk_desc mfgcfg_desc = { + .clks = mfgcfg_clks, + .num_clks = ARRAY_SIZE(mfgcfg_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_mfgcfg[] = { + { .compatible = "mediatek,mt8188-mfgcfg", .data = &mfgcfg_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8188_mfgcfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-mfgcfg", + .of_match_table = of_match_clk_mt8188_mfgcfg, + }, +}; + +builtin_platform_driver(clk_mt8188_mfgcfg_drv); +MODULE_LICENSE("GPL");
--
2.18.0
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