Re: [PATCH v10 02/13] dt-bindings: phy: Add Lynx 10G phy binding
From: Sean Anderson <hidden>
Date: 2023-03-07 19:29:59
Also in:
linux-clk, linux-devicetree, linux-phy, linuxppc-dev
On 3/6/23 14:15, Sean Anderson wrote:
This adds a binding for the SerDes module found on QorIQ processors. Each phy is a subnode of the top-level device, possibly supporting multiple lanes and protocols. This "thick" #phy-cells is used due to allow for better organization of parameters. Note that the particular parameters necessary to select a protocol-controller/lane combination vary across different SoCs, and even within different SerDes on the same SoC. The driver is designed to be able to completely reconfigure lanes at runtime. Generally, the phy consumer can select the appropriate protocol using set_mode. There are two PLLs, each of which can be used as the master clock for each lane. Each PLL has its own reference. For the moment they are required, because it simplifies the driver implementation. Absent reference clocks can be modeled by a fixed-clock with a rate of 0. Signed-off-by: Sean Anderson <redacted> --- (no changes since v9)
I forgot to add Rob's review from last time Reviewed-by: Rob Herring <robh@kernel.org> If another revision is necessary, I will add this. --Sean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel