APSS PLL found in IPQ9574 platform is of type Huayra.
This series adds support for the APSS clock to bump the CPU frequency
above 800MHz.

This series depends on the below patch set
https://lore.kernel.org/linux-arm-msm/20230217083308.12017-1-quic_kathirav@quicinc.com/ (local)

DTS patch depends on the PCIe series
https://lore.kernel.org/linux-arm-msm/20230214164135.17039-1-quic_devipriy@quicinc.com/ (local)

[V2]:
	- Reordered the patches as suggested
	- Dropped [PATCH 6/6] clk: qcom: Fix APSS PLL and RCG Configuration
	  as it was unrelated
	- Detailed Change logs are added to the respective patches
[V1]:
https://lore.kernel.org/linux-arm-kernel/20230113143647.14961-1-quic_devipriy@quicinc.com/ (local)

Devi Priya (5):
  dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible
  clk: qcom: apss-ipq-pll: Enable APSS clock driver in IPQ9574
  dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC
  arm64: dts: qcom: ipq9574: Add support for APSS clock controller
  arm64: defconfig: Enable ipq6018 apss clock and PLL controller

 .../bindings/clock/qcom,a53pll.yaml           |  1 +
 .../mailbox/qcom,apcs-kpss-global.yaml        |  1 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         | 18 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |  1 +
 drivers/clk/qcom/apss-ipq-pll.c               | 19 +++++++++++++++++++
 5 files changed, 40 insertions(+)


base-commit: c068f40300a0eaa34f7105d137a5560b86951aa9
-- 
2.17.1


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