Re: [PATCH v5 1/2] ARM: dts: add GXP Support for fans and SPI

quoted

@@ -52,76 +52,102 @@

cache-level = <2>;
};

- ahb@c0000000 {
+ ahb@80000000 {
compatible = "simple-bus";

address-cells = <1>;

quoted

#size-cells = <1>;
- ranges = <0x0 0xc0000000 0x30000000>;
+ ranges = <0x0 0x80000000 0xf000000>,
+ <0x40000000 0xc0000000 0x40000000>;

In the changelog text for the first patch that moves the
ranges down, it would make sense to describe why this specific
move is done. "to accommodate the SPI and fan driver
register requirements" does not actually tell me why it was
first thought that the bus starts at 0xc0000000 but now starts
at 0x80000000 and has a weird hole.

Please explain how you determined the location of the hole and
the 0x80000000 offset. Are these from the datasheet, from
the hardware design or did you make them up because you thought
this is what I want?

Greetings Arnd,

These are from a specification; I was mapping all the
registers that were not host related, but we need to
include those now.

The AHB section of registers indeed does start at
0x80000000. The layout of AHB is as follows:

0x80000000 - 0xa0000000 are host registers

Then there is a section of registers we do not currently want to
access as it is reserved which is mapped from:

0xa0000000 - 0xc0000000

Then we have more registers ranging from
0xc0000000 - 0xffff0000 that we will be accessing.

Hence, I believe the proper ranges for this would be:

ranges = <0x0 0x80000000 0x20000000
             0x40000000 0xc0000000 0x3fff0000>;

/* 0x80000000 - 0xa0000000 and 0xc0000000 - 0xffff0000 */

quoted

dma-ranges;

Having a 1:1 translation for DMA addresses is actually an indication
that the MMIO addresses on the bus might also be directly
mapped, rather than offset: If AHB addresses 0x0-0x80000000
refer to the local MMIO registers, there is no more room
for addressing RAM in the same addresses.

I believe that this property should no longer be present here.

DMA is in the area before 0x80000000.

Thanks,

-Nick Hawkins



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