Re: [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2

On Thu, Jan 5, 2023 at 2:13 AM John Garry [off-list ref] wrote:

On 05/01/2023 10:05, Jing Zhang wrote:

quoted

quoted

However, for this value of slot, isn't this discoverable from a system register per core? Quoting the sbsa: "The IMPLEMENTATION DEFINED constant SLOTS is discoverable from the system register PMMIR_EL1.SLOTS." Did you consider how this could be used?

This may be a feasible idea. The value of slots comes from the register PMMIR_EL1, which I can read in
/sys/bus/event_source/device/armv8_pmuv3_*/caps/slots. But how do I replace the slots in MetricExpr with the
read slots values? Currently I understand that parameters in metricExpr only support events and constants.

Maybe during runtime we could create a pseudo metric/event for SLOT.

For Intel we do this by just having a different constant for each
architecture. It is fairly easy to add a new "literal", so you could
add a #slots in expr__get_literal:
https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/tree/tools/perf/util/expr.c?h=perf/core#n407
Populating it would be the challenge :-)

Thanks,
Ian

This metric would be created during init, and it always just returns the
value which was read from PMMIR_EL1.

I'm not sure how well that would play will trying to resolve metrics
when building generated pmu-events.c, but I don't think it's all too
difficult to achieve.

Have you actually read this value for the n2 core? Does look correct?

Thanks,
John

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