Re: [PATCH v3 11/12] riscv: Add the Allwinner SoC family Kconfig option
From: Conor Dooley <conor@kernel.org>
Date: 2022-12-08 09:12:28
Also in:
linux-devicetree, linux-riscv, linux-sunxi, lkml
Acked-by: Conor Dooley <conor.dooley@microchip.com> On 8 December 2022 10:02:36 GMT+01:00, Samuel Holland [off-list ref] wrote:
quoted hunk ↗ jump to hunk
Allwinner manufactures the sunxi family of application processors. This includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8 SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs. The first SoC in the sun20i series is D1, containing a single T-HEAD C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM. Most peripherals are shared across the entire chip family. In fact, the ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible with the D1s. This means many existing device drivers can be reused. To facilitate this reuse, name the symbol ARCH_SUNXI, since that is what the existing drivers have as their dependency. Acked-by: Palmer Dabbelt <redacted> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> --- Changes in v3: - ARCH_SUNXI depends on MMU && !XIP_KERNEL Changes in v2: - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing arch/riscv/Kconfig.socs | 10 ++++++++++ 1 file changed, 10 insertions(+)diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..f655dea86d69 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs@@ -26,6 +26,16 @@ config SOC_STARFIVEhelp This enables support for StarFive SoC platform hardware. +config ARCH_SUNXI + bool "Allwinner sun20i SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_THEAD + select SIFIVE_PLIC + select SUN4I_TIMER + help + This enables support for Allwinner sun20i platform hardware, + including boards based on the D1 and D1s SoCs. + config SOC_VIRT bool "QEMU Virt Machine" select CLINT_TIMER if RISCV_M_MODE
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