[PATCH v5 3/4] PCI: j721e: add j784s4 PCIe configuration
From: Matt Ranostay <hidden>
Date: 2022-11-09 08:27:34
Also in:
linux-pci
Subsystem:
pci driver for cadence pcie ip, pci driver for ti dra7xx/j721e, pci native host bridge and endpoint drivers, pci subsystem, the rest · Maintainers:
Vignesh Raghavendra, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Linus Torvalds
Add PCIe configuration for j784s4 platform which has 4x lane support. Tested-by: Achal Verma <redacted> Signed-off-by: Matt Ranostay <redacted> --- drivers/pci/controller/cadence/pci-j721e.c | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index efd065bc0104..83b8100afaff 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c@@ -331,6 +331,21 @@ static const struct j721e_pcie_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct j721e_pcie_data j784s4_pcie_rc_data = { + .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, + .is_intc_v1 = true, + .byte_access_allowed = false, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data = { + .mode = PCI_MODE_EP, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host",
@@ -356,6 +371,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,am64-pcie-ep", .data = &am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = &j784s4_pcie_rc_data, + }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = &j784s4_pcie_ep_data, + }, {}, };
--
2.38.GIT
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