[PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation
From: Marek Vasut <marex@denx.de>
Date: 2022-11-26 22:48:11
Also in:
linux-devicetree, linux-pm
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
The mapping from OCOTP reg DT property to Fusemap Descriptions Table in the datasheet is often unclear. Add a comment to make it easier to find out how it works. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Adam Ford <redacted> Cc: Alice Guo <redacted> Cc: Amit Kucheria <amitk@kernel.org> Cc: Daniel Lezcano <redacted> Cc: Fabio Estevam <festevam@gmail.com> Cc: Krzysztof Kozlowski <redacted> Cc: Li Jun <redacted> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Markus Niebel <redacted> Cc: NXP Linux Team <redacted> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Rafael J. Wysocki <rafael@kernel.org> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Zhang Rui <rui.zhang@intel.com> Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++---- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++--- 4 files changed, 65 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 423cb36cbcd53..513c2de0caa15 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi@@ -563,15 +563,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 312e3abc35ea8..068f599cdf757 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi@@ -564,15 +564,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mn_uid: unique-id@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c9459ed21b243..ddcd5e23ba47d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi@@ -426,19 +426,32 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mp_uid: unique-id@8 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x8 0x8> describes fuses 0x420 and + * 0x430). + */ + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - eth_mac1: mac-address@90 { + eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; - eth_mac2: mac-address@96 { + eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 2b6d3f4ff5d93..8a2ec90b493d9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi@@ -593,15 +593,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mq_uid: soc-uid@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = <ADDR SIZE>; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };
--
2.35.1
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