On Mon, Oct 31, 2022 at 5:40 PM Kevin Hilman [off-list ref] wrote:

Hi Balsam,


bchihi@baylibre.com writes:

quoted

From: Balsam CHIHI <redacted>

On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.

This is the original patch series proposed by Fabien Parent [off-list ref].
"https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/ (local)"

Changelog:
Changes in v2 :
        - Rebase on top of 6.1.0-rc1-next-20221020
        - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
        - Add mt8365_set_clr_mode() callback

nit: subject of cover letter should also include "pinctrl: mediatek:"
prefix.  Also note that you're missing the word "PATCH" in all of the
subjects.

Tip: If you use `git format-patch`, you can just pass `-v2` on the
cmdline and it will create the prefixes for you automatically.

Hi Kevin,

Well received.
I will fix these issues in the next version/resend.
Thank you so much for the review!

Balsam.

Kevin

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