[PATCH v1 1/2] arm64/cpufeature: Add feature detection for fine grained traps
From: Mark Brown <broonie@kernel.org>
Date: 2022-10-27 20:56:02
Also in:
kvmarm
Subsystem:
arm64 port (aarch64 architecture), the rest · Maintainers:
Catalin Marinas, Will Deacon, Linus Torvalds
Virtualisation support for SME depends on FEAT_FGT since it uses fine grained traps to control access to SMPRI_EL1 and (for nVHE) TPIDR2_EL0 but systems have been encountered which implement SME without VHE. In order to work around such systems we need to detect the absence of FEAT_FGT, add detection in the cpufeature code. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 12 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6062454a9067..8ded72a8ccee 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c@@ -2590,6 +2590,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .min_field_value = 1, }, + { + .desc = "Fine Grained Traps", + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .capability = ARM64_HAS_FGT, + .sys_reg = SYS_ID_AA64MMFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR0_EL1_FGT_SHIFT, + .field_width = ID_AA64MMFR0_EL1_FGT_WIDTH, + .min_field_value = ID_AA64MMFR0_EL1_FGT_IMP, + .matches = has_cpuid_feature, + }, #ifdef CONFIG_ARM64_SME { .desc = "Scalable Matrix Extension",
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index f1c0347ec31a..2553c7559412 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps@@ -23,6 +23,7 @@ HAS_DCPOP HAS_E0PD HAS_ECV HAS_EPAN +HAS_FGT HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5
--
2.30.2
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