[PATCH v2 1/3] PCI: j721e: Add PCIe 4x lane selection support
From: Matt Ranostay <hidden>
Date: 2022-09-26 17:57:14
Also in:
linux-pci
Subsystem:
pci driver for cadence pcie ip, pci driver for ti dra7xx/j721e, pci native host bridge and endpoint drivers, pci subsystem, the rest · Maintainers:
Vignesh Raghavendra, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Linus Torvalds
Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Cc: Kishon Vijay Abraham I <redacted> Signed-off-by: Matt Ranostay <redacted> --- drivers/pci/controller/cadence/pci-j721e.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index a82f845cc4b5..d9b1527421c3 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c@@ -43,7 +43,6 @@ enum link_status { }; #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) #define GENERATION_SEL_MASK GENMASK(1, 0)
@@ -207,11 +206,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, { struct device *dev = pcie->cdns_pcie->dev; u32 lanes = pcie->num_lanes; + u32 mask = GENMASK(8, 8); u32 val = 0; int ret; + if (lanes == 4) + mask = GENMASK(9, 8); + val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n");
--
2.38.0.rc0.52.gdda7228a83
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