[PATCH v3 03/11] arm64: dts: mt8195: Add SCP core 1 node
From: Tinghan Shen <hidden>
Date: 2022-09-27 03:00:36
Also in:
linux-devicetree, linux-media, linux-mediatek, linux-remoteproc, lkml
Subsystem:
arm/mediatek soc support, the rest · Maintainers:
Matthias Brugger, AngeloGioacchino Del Regno, Linus Torvalds
Add the 2nd core(core 1) of MT8195 dual-core SCP to devicetree file. Reserve some SRAM spaces for the core 1 image. Signed-off-by: Tinghan Shen <redacted> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..48d457bd39b8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi@@ -760,12 +760,24 @@ scp: scp@10500000 { compatible = "mediatek,mt8195-scp"; - reg = <0 0x10500000 0 0x100000>, + reg = <0 0x10500000 0 0xa0000>, <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>; reg-names = "sram", "cfg", "l1tcm"; interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x105a0000 0 0x105a0000 0x20000>; + + scp_c1: scp-c1@105a0000 { + compatible = "mediatek,mt8195-scp-core"; + reg = <0x105a0000 0x20000>; + reg-names = "sram"; + interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; }; scp_adsp: clock-controller@10720000 {
--
2.18.0
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