Hi Krzysztof,

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: Tuesday, August 23, 2022 6:17 PM
To: Potthuri, Sai Krishna <sai.krishna.potthuri@amd.com>; Rob Herring
[off-list ref]; Krzysztof Kozlowski
[off-list ref]; Michal Simek
[off-list ref]; Borislav Petkov [off-list ref]; Mauro
Carvalho Chehab [off-list ref]; Tony Luck [off-list ref];
James Morse [off-list ref]; Robert Richter [off-list ref]
Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
kernel@vger.kernel.org; linux-edac@vger.kernel.org;
saikrishna12468@gmail.com; git (AMD-Xilinx) [off-list ref]; Shubhrajyoti
Datta [off-list ref]
Subject: Re: [PATCH v2 1/2] dt-bindings: edac: Add bindings for Xilinx ZynqMP
OCM

On 22/08/2022 14:58, Sai Krishna Potthuri wrote:

quoted

From: Shubhrajyoti Datta <redacted>

Add bindings for Xilinx ZynqMP OCM controller.

Signed-off-by: Shubhrajyoti Datta <redacted>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
---
 .../bindings/edac/xlnx,zynqmp-ocmc.yaml       | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml

diff --git
a/Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml
b/Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml
new file mode 100644
index 000000000000..6389fcb7ed69

--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml

@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/xlnx,zynqmp-ocmc.yaml#

Filename should be based on compatible, so xlnx,zynqmp-ocmc-1.0.yaml

I will fix in v3, Just want to know in case if we have multiple compatibles, 
how to handle such cases?

quoted

+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynqmp OCM(On-Chip Memory) Controller

So this is a memory controller, then please put the bindings in the memory-
controllers directory.

I will fix in v3.

quoted

+
+maintainers:
+  - Shubhrajyoti Datta [off-list ref]
+  - Sai Krishna Potthuri [off-list ref]
+
+description: |
+  The OCM supports 64-bit wide ECC functionality to detect multi-bit
+errors
+  and recover from a single-bit memory fault.On a write, if all bytes
+are
+  being written, the ECC is generated and written into the ECC RAM
+along with
+  the write-data that is written into the data RAM. If one or more
+bytes are
+  not written, then the read operation results in an correctable
+error or
+  uncorrectable error.
+
+properties:
+  compatible:
+    const: xlnx,zynqmp-ocmc-1.0
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+unevaluatedProperties: false

Instead this should be:
additionalProperties: false

I will fix in v3.

quoted

+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    memory-controller@ff960000 {
+      compatible = "xlnx,zynqmp-ocmc-1.0";
+      reg = <0xff960000 0x1000>;
+      interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;

What does 0 stand for? I commented about it already.

I will fix in v3.

Regards
Sai krishna

quoted

+    };

Best regards,
Krzysztof

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