On Tue, Aug 23, 2022 at 11:22:08AM +0300, Krzysztof Kozlowski wrote:

On 23/08/2022 11:17, Krzysztof Kozlowski wrote:

quoted

On 22/08/2022 22:07, Serge Semin wrote:

quoted

The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC:
the CSRs layout is absolutely different and it doesn't has IRQ unlike DW
uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there is
no any reason to have these controllers described by the same bindings.
Thus let's split them up.

While at it rename the original Synopsys uMCTL2 DT-schema file to a more
descriptive - snps,dw-umctl2-ddrc.yaml and add a more detailed title and
description of the device bindings.

Filename should be based on compatible, so if renaming then
snps,ddrc-3.80a.yaml or snps,ddrc.yaml... which leads to original
filename anyway. Therefore nack for rename.

BTW, if you perform renames, generate patches with proper -M/-C/-B
arguments so this is detected.

quoted

Signed-off-by: Serge Semin <redacted>
--->  .../snps,dw-umctl2-ddrc.yaml                  | 51 +++++++++++++

This is a mess. I did not get any cover letters, any other patches any
description of relation between this and your other one.

It seems you make independent and conflicting changes to the same file,
so this has to be properly organized.

Send entire patchset with cover letter with description of all
dependencies to all maintainers.

This is unreviewable now, so a no.

And also untestable by Rob's bot, so will have to wait.

For what reason it's untestable? The patch has no dependencies from
any other patchset.

-Sergey

I found the cover letters, somehow they got buried in inbox.

Best regards,
Krzysztof

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