[PATCH 19/33] dmaengine: at_hdmac: Don't allow CPU to reorder channel enable
From: Tudor Ambarus <hidden>
Date: 2022-08-20 12:59:36
Also in:
dmaengine, lkml, stable
Subsystem:
dma generic offload engine subsystem, microchip at91 dma drivers, the rest · Maintainers:
Vinod Koul, Ludovic Desroches, Linus Torvalds
at_hdmac uses __raw_writel for register writes. In the absence of a
barrier, the CPU may reorder the register operations.
Introduce a write memory barrier so that the CPU does not reorder the
channel enable, thus the start of the transfer, without making sure that
all the pre-required register fields are already written.
Fixes: dc78baa2b90b ("dmaengine: at_hdmac: new driver for the Atmel AHB DMA Controller")
Reported-by: Peter Rosin <redacted>
Cc: stable@vger.kernel.org
Signed-off-by: Tudor Ambarus <redacted>
Link: https://lore.kernel.org/lkml/13c6c9a2-6db5-c3bf-349b-4c127ad3496a@axentia.se/ (local)
---
drivers/dma/at_hdmac.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 825a29ede35e..1cb0d26d30ed 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c@@ -691,6 +691,8 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) channel_writel(atchan, DPIP, FIELD_PREP(ATC_DPIP_HOLE, first->dst_hole) | FIELD_PREP(ATC_DPIP_BOUNDARY, first->boundary)); + /* Don't allow CPU to reorder channel enable. */ + wmb(); dma_writel(atdma, CHER, atchan->mask); vdbg_dump_regs(atchan);
--
2.25.1
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