On Sat, 30 Jul 2022 at 01:56, Stephen Boyd [off-list ref] wrote:

Quoting Tomer Maimon (2022-07-24 02:06:54)

quoted

On Sat, 23 Jul 2022 at 06:02, Stephen Boyd [off-list ref] wrote:

quoted

Furthermore, in DT, reg properties aren't supposed to overlap. When that
happens it usually indicates the DT is being written to describe driver
structure instead of the IP blocks that are delivered by the hardware
engineer. In this case it sounds like a combined clk and reset IP block
because they piled all the SoC glue stuff into a register range. Are
there more features in this IO range?

No, this range only combined the reset and clock together, but it
combined in a way that we cannot split it to two or even three
different registers...

Because it is jumbled in some range?

Yes.

quoted

I do see a way to combine the clock and the reset driver, the NPCM
reset driver is serving other NPCM BMC's.
Should we use regmap to handle the clock registers instead of ioremap?

Sure? Using regmap or not looks like a parallel discussion. How does it
help use platform APIs?

I mean to use regmap API instead of platform API for handing the clock
and reset registers.
the regmap API gives only one user access to R/W (lock).
I will be happy to get more suggestions, on how should we solve this situation.

Thanks,

Tomer

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