Thread (57 messages) 57 messages, 5 authors, 2022-09-11

Re: [RFC v8 net-next 00/16] add support for VSC7512 control over SPI

From: Colin Foster <colin.foster@in-advantage.com>
Date: 2022-05-14 22:00:22
Also in: linux-gpio, netdev

On Mon, May 09, 2022 at 05:13:05PM +0000, Vladimir Oltean wrote:
Hi Colin,

On Sun, May 08, 2022 at 11:52:57AM -0700, Colin Foster wrote:
quoted
		mdio0: mdio0@0 {
This is going to be interesting. Some drivers with multiple MDIO buses
create an "mdios" container with #address-cells = <1> and put the MDIO
bus nodes under that. Others create an "mdio" node and an "mdio0" node
(and no address for either of them).

The problem with the latter approach is that
Documentation/devicetree/bindings/net/mdio.yaml does not accept the
"mdio0"/"mdio1" node name for an MDIO bus.
I'm starting this implementation. Yep - it is interesting.

A quick grep for "mdios" only shows one hit:
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts

While that has an mdios field (two, actually), each only has one mdio
bus, and they all seem to get parsed / registered through
sja1105_mdiobus_.*_register.


Is this change correct (I have a feeling it isn't):

ocelot-chip@0 {
    #address-cells = <1>;
    #size-cells = <0>;

    ...

    mdio0: mdio@0 {
        reg=<0>;
        ...
    };

    mdio1: mdio@1 {
        reg = <1>;
        ...
    };
    ...
};

When I run this with MFD's (use,)of_reg, things work as I'd expect. But
I don't directly have the option to use an "mdios" container here
because MFD runs "for_each_child_of_node" doesn't dig into
mdios->mdio0...
quoted
			compatible = "mscc,ocelot-miim";
			#address-cells = <1>;
			#size-cells = <0>;

			sw_phy0: ethernet-phy@0 {
				reg = <0x0>;
			};

			sw_phy1: ethernet-phy@1 {
				reg = <0x1>;
			};

			sw_phy2: ethernet-phy@2 {
				reg = <0x2>;
			};

			sw_phy3: ethernet-phy@3 {
				reg = <0x3>;
			};
		};

		mdio1: mdio1@1 {
			compatible = "mscc,ocelot-miim";
			pinctrl-names = "default";
			pinctrl-0 = <&miim1>;
			#address-cells = <1>;
			#size-cells = <0>;

			sw_phy4: ethernet-phy@4 {
				reg = <0x4>;
			};

			sw_phy5: ethernet-phy@5 {
				reg = <0x5>;
			};

			sw_phy6: ethernet-phy@6 {
				reg = <0x6>;
			};

			sw_phy7: ethernet-phy@7 {
				reg = <0x7>;
			};
		};
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